Code Generation for ILP Architectures with Partitioned Register Banks

当前微处理器的设计方向是朝着提供更大指令级并行性(ILP)的芯片发展。不幸的是，大量的ILP硬件和激进的指令调度技术对机器的寄存器资源提出了很大的要求。由于ILP水平很高，很难维持一个单一的寄存库。这种寄存器库所需的端口数严重阻碍了访问时间，并且可能需要过多的芯片空间。因此，高ILP结构需要具有有限连接性的分区寄存器组。然而，当从另一寄存器库获取数据时，分区寄存器库的使用抑制了ILP。这项研究解决了以机器无关的方式减少与分区寄存器库相关的开销的方法。具体地说，本研究主要解决了以下几个问题：1.提出了一种与机器无关的通信和并行程序表示方法。2.在机器的寄存器库之间划分数据的新算法。3.在指令级暴露数据并行性的循环转换。4.允许一组功能单元访问单个寄存器库的集群方案。作为这项研究的结果，由于与分区寄存器库相关的较低开销，较高水平的ILP将更具吸引力。

Current microprocessor design directions are towards chips that provide greater instruction-level parallelism (ILP). Unfortunately, large amounts of ILP hardware and aggressive instruction scheduling techniques put large demands on a machine's register resources. With large levels of ILP, it is difficult to maintain a single register bank. The number of ports required for such a register bank severely hampers access time and may require too much chip space. As a result,partitioned register banks with limited connectivity are needed forhigh ILP architectures. The use of partitioned register banks,however, inhibits ILP when data is fetched from another register bank. This research addresses methods to reduce the overhead associated with partitioned register banks in a machine-independent fashion. Specifically, the research addresses the following issues 1. A machine-independent program representation modeling communication and parallelism. 2. New algorithms to partition data amongst a machine's register banks. 3. Loop transformations that expose the data parallelism at the instruction level. 4. Clustering schemes that allow a group of functional units to access a single register bank. As a result of this research, higher levels of ILP will be more attractive due to a lower overhead associated with partitioned register banks.