Adaptive Balanced Computing Architecture

应用程序，如多媒体处理、数字信号、图像和视觉处理以及科学计算，产生结构化和重复的计算任务，表现出不同程度的指令级并行性（ILP）。此外，计算某些函数的需求及其资源需求随应用程序和时间而变化。该项目的总体目标是开发和使用新的想法，如可重构功能单元（FUs）、缓存存储器和可重构总线架构，以实现平衡计算，即将计算带宽与内存带宽相匹配。该研究将解决架构设计中的问题，允许资源的重新配置，使以下架构级别参数动态可变：FUs的数量和类型，片上寄存器和缓存的数量，片上存储资源与FUs数量动态交易的能力，以及这些单元之间的互连性。将开发具有可重构逻辑块的处理器核心，使体系结构适应应用程序的计算和内存带宽需求。将重构方案集成到片上FUs和处理器芯片上的缓存存储器中的效果也将进行研究和评估。ABC（自适应平衡计算）架构的高级设计将被开发和分析。预计研究结果将显著提高计算效率。

Applications, such as multimedia processing, digital signal, image and vision processing, and scientific computing, generate computation tasks that are structured and repetitive exhibiting varying degree of instruction-level parallelism (ILP). Moreover, the demands to compute certain functions and theirresource needs vary with applications and time. The overall goal of this project is to develop and use novel ideas such as reconfigurable functional units (FUs), cache memory, and reconfigurable bus architectures to achieve balanced computing, i.e. match the computing bandwidth to the memory bandwidth. The research will address issues in designing architectures that allow reconfiguration of resources to make the following architecture level parameters dynamically variable: number and types of FUs, amount of on-chip register and cache memory, an ability to trade the on-chip memory resources with the numberof FUs dynamically, and the interconnectivity between these units. A processor core with reconfigurable logic blocks to make the architecture adaptive to the applications' computing and memory bandwidth needs will be developed. Effects of integrating reconfiguration schemes into the on-chip FUs and cache memorieson a processor chip will also be studied and evaluated. A high-level design for the ABC (Adaptive Balanced Computing) architecture will be developed and analyzed. It is expected that the research results will significantly improve the efficiency of computation.