NSF-CNPq Collaborative Research on Design Environments for Application-Specific Programmable Processors

本研究是在嵌入式系统设计工具，以建立定制的专用指令处理器（ASIP）架构，是没有更大，或没有比必要的复杂。开发ASIP不仅需要硬件设计，而且需要使用一套评估工具，如汇编器、编译器和模拟器。这项调查使用的处理器描述，作为一个共同的出发点，这些工具的发展，以及硬件综合。MIT正在开发的ISDL语言正是为了这个目的而被用于开发一个完整的软件开发环境，以及硬件生成。模拟器用于获得应用程序代码的时钟周期估计，并评估整体架构性能。处理器数据路径的合成使硬件生成成为可能，并提供准确的周期时间估计。为了支持软件编译，一个有针对性的汇编程序，代码生成器和优化器将被开发，作为输入接收ISDL中的机器描述，以及要编译到所描述的机器上的程序。在合理的时间内生成最高质量代码的新优化正在评估中。我们的可重定向编译器的基础是SPAM，一个嵌入式编译器框架，已开发的MIT，普林斯顿大学和UNICAMP，巴西的研究人员。在许多情况下，应用程序代码不是用高级编程语言编写的，并且有必要处理汇编或遗留代码。因此，正在研究优化二进制到二进制翻译的自动方法。为此，将遗留的二进制/汇编代码反编译为编译器基础结构使用的中间形式，然后使用优化编译器技术为目标体系结构生成高质量的汇编。

This research is on embedded systems design tools for building customapplication-specific instruction processor (ASIP) architectures that are nobigger, or no more complex than necessary. Developing an ASIP, not onlyrequires hardware design, but also requires the use of a set of evaluationtools such as an assembler, compiler and simulator. This investigation usesa processor description to serve as a common starting point for thedevelopment of these tools, as well as for hardware synthesis. The ISDLlanguage, being developed at MIT, for exactly this purpose is being used indeveloping a complete software development environment, as well as hardwaregeneration. The simulator is used to obtain clock cycle estimates onapplication code, and to evaluate the overall architecture performance.Synthesis of processor datapaths enables hardware generation and providesaccurate, cycle-time estimates. To support software compilation, aretargetable assembler, code generator and optimizer will be developed thatreceive as input both a machine description in ISDL, and the program to becompiled onto the described machine. New optimizations to produce code ofthe highest quality in a reasonable amount of time are being evaluated. Thebase of our retargetable compiler is SPAM, an embedded compiler frameworkthat has been developed by researchers at MIT, Princeton and UNICAMP,Brazil. In many cases, application code is not written in high-levelprogramming languages, and it is necessary to deal with assembly or legacycode. Thus automatic methods for optimized binary-to-binary translation arebeing investigated. To do this, the legacy binary/assembly code isdecompiled to intermediate forms used by our compiler infrastructure andthen using the optimizing compiler technology to generate high-qualityassembly for the target architecture.