Test Techniques for Deep Submicron Devices

本研究的重点是发展深亚微米缺陷的建模、分析和矢量生成技术，特别是将电源噪声、互连串扰故障、连续性和开路故障建模为统计延迟故障。建模过程的结果被用来选择测试评估和测试生成的目标延迟故障。本计画进一步研究所选目标延迟故障的向量产生技术。测试不仅激活和传播故障，而且会引起各种最坏情况的噪声，使得沿敏感路径的传播延迟沿着最大化。此外，DFT的要求和规则，以消除或减少某些噪声故障的概率和简化这些故障的矢量生成正在探索。

This research focuses on developing modeling, analysis and vectorgeneration techniques for some of the emerging deep submicron defects.Specifically, this project is developing techniques to model the excessivepower supply noise, the interconnect crosstalk faults and the resistiveshort and open faults as statistical delay faults. The results of themodeling process are being used to select target delay faults for testevaluation and test generation. This project further investigates vectorgeneration techniques for the selected target delay faults. The tests notonly activate and propagate the faults but also cause various worst-casenoises such that the propagation delay along the sensitized path ismaximized. Furthermore, DFT requirements and rules for eliminating orreducing the probability of having certain noise faults and for simplifyingvector generation for these faults are being explored.