Novel Giga Sampling Analog-to-Digital Conversion for Direct Digital Receiver

ECS-9979341FengA系列语音与数据在设备和网络层面的融合，无线与有线网络的融合，以及网络架构向分组交换的融合，直接影响了60 GHz皮蜂窝技术在大市场的快速需求。NSF 99-68的目标是解决这一需求，并开发第四代（4G）高信息容量无线移动通信系统，其特点是高吞吐量、混合流量、高数据速率和高达60 GHz的宽带。我们建议研究如图1所示的直接转换数字接收机，其中60 GHz信号将通过HBT VCO技术混合为1至2 GHz中频信号。数字接收机可用于接收任何类型的调制标准，包括模拟（AM， FM）或数字（QPSK， QAM， FSK， GMSK等）。此外，同一接收器可用于模拟和数字调制信号。使用数字下变频（DDQ）和称为信道转换器的滤波芯片进行调谐。由于直接转换数字接收机直接从调制带通信号进行模拟到数字的转换，以最大限度地提高调制信号的带宽，因此用户可以消除大部分前端RF组件，并使用更可靠的数字组件执行相同的功能。然后将由此产生的高速数据流呈现给数字解调器，该数字解调器分离各个信道并提取调制信息。无线通信接收器集成电路的设计工作主要集中在开发合适的ADC架构和高效的电路实现技术以及相关的器件技术。然而，由于速度和分辨率的限制，目前报告的结果不足以满足4G无线移动通信应用的要求。4G无线移动通信系统需要高数据速率和宽带宽。为了满足4G的要求，ADC的输入带宽应该足够平坦，以防止产生的数字表示中的失真和非线性。因此，高分辨率、高速的模数转换器（ADC）成为成功开发该通信系统的最重要的硬件元件。因此，我们提出了一种新的千兆采样模数转换器，其规格如下：2.5 W功耗，15位分辨率，90 dB SFDR, 84 dB SINAD（信噪比和失真比），以及1.5 GHz下的14 ENOB，采用新颖的ADC架构，基于折叠和插值的15位分幅a /D转换器。该ADC需要开发200 GHz fT InGaP/GaAs或InGaAs/InP HBT工艺。通过实现这些规范，我们可以达到相当于22.5千兆比特/秒的数据速率。目前没有与建议目标兼容的现有ADC产品。

ECS-9979341FengA series convergence of voice with data at device and network levels, and wireless with wireline network, and network architectures converging on packet switching have direct implications for the rapid need of large market at 60 GHz picocelltechnology. The goal of NSF 99-68 is to address this need and to develop fourth generation (4G) high information capacity wireless mobile communication systems which are characterized by high throughput, mixed traffic, high data rates and wide bandwidth up to 60 GHz. We propose to study the direct conversion digital receiver as shown in Fig. 1 where the 60 GHz signal will be mixed down to I to 2 GHz IF signal via HBT VCO technology. The digital receivers can be used to receive any type of modulation standard including analog (AM, FM) or digital (QPSK, QAM, FSK, GMSK, etc.). Furthermore, the same receiver can be used for both analog and digitally modulated signals. Tuning is performed using a digital down converter (DDQ and filter chip called a channelizer. Since the direct conversion digital receiver performs analog to digital conversion directly from the modulated bandpass signal to maximize the modulated signal bandwidth, the user can eliminate most of the front-end RF components and perform the same function using more reliable digital components. The high speed data stream thus created is then presented to a digital demodulator which separates the individual channels and extracts the modulated information. The efforts in the design of integrated circuits for wireless communication receivers have focused on developing suitable ADC architectures and efficient circuit implementation techniques as well as associated device technologies. However, results reported so far have been insufficient to meet the required specification for 4G wireless mobile communication application due to their speed and resolution limitations.4G wireless mobile communication systems require high-data rates as well as wide bandwidth. To meet 4G requirement, the input bandwidth of the ADC should be sufficiently flat to prevent distortions and non-linearities in the resulting digital representation. Thus a high-resolution, high-speed analog to digital converter (ADC) becomes the most important hardware element in successfully developing this communication system. Therefore, we propose a new Giga-sampling analog to digital converter with the following specifications: 2.5 W power consumption, 15 bit resolution, 90 dB SFDR, 84 dB SINAD (Signal to Noise and Distortion Ratio), and 14 ENOB at 1.5 GHz using a novel ADC architecture, the folding and interpolation based 15 bit subranging A/D converter. This ADC requires the development of 200 GHz fT InGaP/GaAs or InGaAs/InP HBT process. By achieving these specifications, we may reach data rates equivalent to 22.5 Giga bits/sec. No existing ADC product is currently available which is compatible with the proposed target.