VLSI Arithmetic Logic Schemes and Low-Power High-Performance Circuits for Parallel and Reconfigurable Computations

建议：CCR 0073469标题：新的VLSI算术逻辑方案和低功耗高性能电路用于并行和可重构计算PI：荣线性摘要本研究研究了几种基本的并行和可重构算术和基本功能单元的设计、体系结构和算法。研究中使用了最近发展起来的非二进制VLSI移位开关逻辑方案和低功耗高性能电路。采用新型逻辑和积木电路的专用处理器在VLSI设计中显示出了优越性，包括高速大数组乘法器、可重构内积处理器和可重构矩阵乘法器。为所有这些计算开发一个动态可重新配置的平台是该项目的主要目标。新的逻辑方案主要使用移位开关并行计数器单元作为逻辑运算符，以及表示从0到3的值的4位数字信号作为逻辑操作数，其中在最坏的情况下，4个信号位中只有2个位在任何逻辑级受到值变化的影响。这是用来简化电路设计和降低功耗。这项研究的主要重点是进一步探索逻辑方案和电路的特性和优势，并开发并行和可重构计算的优越应用。预计将对下一代微处理器和SOC设计产生重大影响。

Proposal: CCR 0073469Title: New VLSI Arithmetic Logic Schemes and Low-Power High-Performance CircuitsFor Parallel and Reconfigurable ComputationsPI: Rong LinABSTRACTThis research investigates several basic parallel and reconfigurable arithmetic and elementary functional unit designs, architectures and algorithms. Recently developed non-binary VLSI shift switch logic schemes and low-power high-performance circuits are used for the study. A set of application specific processors, using the novel logic and the building-block circuits, has demonstrated superiority in VLSI design, which includes high-speed large-size array multipliers, reconfigurable inner product processors and reconfigurable matrix multipliers. Development of a dynamically reconfigurable platform for all of these computations is a major target of this project. The new logic schemes primarily employ shift switch parallel counter units as logic operators, and 4-bit digital signals, representing values ranging from 0 to 3, as logic operands, where only 2-out-of-4 signal bits are subject to value-change at any logic stage in the worst case. This is used to simplify the circuit designs and to reduce the power-dissipation. The main focus of this research is to further explore the properties and advantages of the logic schemes and circuits, and to develop superior applications for parallel and reconfigurable computations. A significant impact on the next generation of microprocessors and SOC designs is expected.