Interconnect Length Prediction and Length Prediction Driven Placement

复杂的ULSI设计将受到无数互连问题的困扰，这些问题可能需要多次设计迭代才能满足时序、功率、面积和噪声规格。为了科普这种互连困境，目前的晶体管为中心的VLSI设计流程必须演变成一个以互连为中心的设计流程，但是，这种设计流程的发展，它必须准确地预测在设计的最早阶段的逻辑megacell的性能互连的影响。这项研究工作的重点是在逻辑设计过程中开发一个给定的网表中的每个网络的长度的准确预测。这项工作的新颖之处在于，一个随机的线长分布模型，这已部分开发的主要研究者，被用来帮助在这一预测。此外，预测方法，使设计师能够选择一组可能的布线配置的强调。这种预测方法的一个组成部分是将导线长度预测纳入长度预测驱动的布局算法。这项研究的意义在于，高度准确的线长预测可以大大提高早期时序分析的准确性，并为设计人员提供更大的灵活性，以找到解决方案，克服即将到来的互连限制。

Complex ULSI designs will be plagued by a myriad of interconnects problems that could require many design iterations to meet timing, power, area, and noise specifications. To cope with this interconnect dilemma, the current transistor-centric VLSI design flow must evolve into an interconnect-centric design flow; however, for this design flow to develop it must accurately predict the impact of interconnects on the performance of logic megacells at the earliest stages of design. This research effort is focused on developing an accurate prediction of the length of each net in a given netlist during logic design. The novel aspect of this work is that a stochastic wire length distribution model, which has been developed in part by the principal investigator, is being used to aid in this prediction. In addition, prediction methodologies that give the designer the ability to choose from a set of possible wiring configurations is emphasized. An integral part of this prediction methodology is the incorporation of the wire length predictions into length prediction driven placement algorithms. The significance of this proposed research is that highly accurate wire length predictions could substantially enhance the accuracy of early timing analysis and give the designer greater flexibility in finding solutions to overcome impending interconnect limits.