CAREER: Interconnect Dominant ULSI Designs: A New Paradigm for 21st Century IC Design and Education

该方案解决了高速通信网络取代片上全局和半全局互连的适用性。具有有限数量的门和导线的宏单元通过通信网络连接起来。实验表明，限制每个宏单元的栅极数量可以减少电路实现所需的金属层数量。此外，提出了三维互连标准单元设计的基础研究，以实现互连相关参数的可预测性。这是一项教育和研究相结合的努力。目标是克服超大规模集成（ULSI）互连所带来的限制。正在进行的基础研究是：(1)高速片上通信网络的适用性，以取代专用的半全局和全局互连，用于微处理器，ASIC或SoC设计；(2)结合新的3-D互连标准电池设计，可预测电容和电感，从而可预测时间、功率和面积；(3) 5-12年级的教育工具，促进学生发现当前和未来微处理器设计中的问题和机会。

This proposal addresses the applicability of high-speed communication networks to replace on-chip global and semi-global interconnects. Macrocells with the limited number of gates and wires are connected through the communication network. Limiting the number of gates per macrocell is shown experimentally to reduce the number of metal layers needed for circuit implementation. Additionally a basic research on 3-D interconnect standard cell design for predictability of interconnect related parameters is proposed. This is a combined educational and research effort. The goal is to overcome the limitations imposed by ultra-large scale integrated (ULSI) interconnects. Basic research is being conducted is in: (1) the applicability of high-speed on-chip communication networks to replace dedicated semi-global and global interconnects for use in microprocessor, ASIC, or SoC designs; (2) the incorporation of new 3-D interconnect standard cell design for capacitance and inductance predictability and hence timing, power, and area predictability; and (3) educational tools for grades 5-12 that promote student discovery in the problems and opportunities in present and future microprocessor design.