CAREER: Interconnect Dominant ULSI Designs: A New Paradigm for 21st Century IC Design and Education

该建议解决了高速通信网络取代片上全局和半全局互连的适用性。门和线数量有限的宏单元通过通信网络连接。通过实验证明，限制每个宏单元的栅极数量可以减少电路实现所需的金属层的数量。此外，还提出了互连相关参数可预测性的三维互连标准单元设计的基础研究。这是一项教育和研究相结合的努力。其目标是克服超大规模集成(ULSI)互连带来的限制。目前正在进行的基础研究包括：(1)高速片上通信网络的适用性，以取代用于微处理器、ASIC或SoC设计的专用半全局和全局互连；(2)采用新的3-D互连标准单元设计，以实现电容和电感的可预测性，从而实现定时、功率和面积的可预测性；以及(3)5-12年级的教育工具，旨在促进学生发现目前和未来微处理器设计中的问题和机会。

This proposal addresses the applicability of high-speed communication networks to replace on-chip global and semi-global interconnects. Macrocells with the limited number of gates and wires are connected through the communication network. Limiting the number of gates per macrocell is shown experimentally to reduce the number of metal layers needed for circuit implementation. Additionally a basic research on 3-D interconnect standard cell design for predictability of interconnect related parameters is proposed. This is a combined educational and research effort. The goal is to overcome the limitations imposed by ultra-large scale integrated (ULSI) interconnects. Basic research is being conducted is in: (1) the applicability of high-speed on-chip communication networks to replace dedicated semi-global and global interconnects for use in microprocessor, ASIC, or SoC designs; (2) the incorporation of new 3-D interconnect standard cell design for capacitance and inductance predictability and hence timing, power, and area predictability; and (3) educational tools for grades 5-12 that promote student discovery in the problems and opportunities in present and future microprocessor design.