MRI: Acquisition of RF/Mixed Signal Test Equipment for Ultra-High Frequency System-on-Chip Applications

信息革命的主要驱动力是先进的硅加工。因此，系统设计正在经历根本性的变化，从多芯片解决方案转向片上系统(SOC)解决方案。然而，正如国家科学基金会最近关于先进VLSI系统的规划研讨会所指出的那样，与集成到SoC解决方案中的这些不同资源相关的测试和测量理论和实践是一个重大的悬而未决的问题，可能会极大地限制未来的进步。工艺技术的进步提供了全新的器件类型，以及相应的设计挑战和测试和测量需求。UW目前正在开发的这种系统的一个例子是人/机换能器芯片-通用换能器芯片，这是能够向无处不在的无线网络提供语音识别接口的单个集成系统。这样的系统很可能成为一系列新应用的标准接口形式，从智能家居和智能测试台到无处不在的高性能计算结构。然而，为了实现这一潜力，必须解决多个测试和测量问题：o必须在ISM(2.4 GHz)和UNFL(5.6-5.8 GHz)频段测试和表征射频收发器，以满足广泛的新兴无线标准。因此，必须测试低功耗、高性能的无线硬件实现，并且必须开发和验证测量技术，以用于未来17 GHz LMDS频段的SoC应用，以及以上必须支持异质单芯片集成和测试和测量，从而允许制造RF、模拟、高性能数字、在单个硅片中实现可重新配置的子系统本提案中包含的基础设施使人们能够在超高频SoC系统商业化前数年对其进行测试和测量的未来进行调查。我们将寻求开发和演示一种测试和测量方法，该方法可以为众多设计领域提供多种不同资源类型的好处。作为这些努力的最初驱动力，我们将对人机传感器芯片进行表征，以寻求指导未来片上系统设计和测试方法的发展。它通常代表着未来的SoC系统，这些系统将以越来越高的频率和越来越高的复杂性运行。为了支持此类尖端硅系统的设计，我们将开发创新技术来处理大量测试问题：o验证将射频和模拟组件集成到未来超低压SoC设计中的技术。o验证支持这些系统的高性能、高能效数字逻辑系列。o针对复杂、异质系统的集成测试方法，通过片上和片外超高频测试环境的最佳组合提供完整的系统测试。除了开发测试和测量SoC芯片设计的新方法外，我们还将开发创新技术，以培养未来的高频SoC设计人员。通过提供包括高频测试和测量在内的综合课程以及即时学习环境，我们将帮助培养能够利用这些全新的设计技术和机会的系统架构师。

The primary driver of the information revolution is advanced silicon processing. Consequently, system design is undergoing a fundamental change, moving from multiple chip solutions to system-on-a-chip (SOC) solutions. However, as was noted in the National Science Foundation's recent planning workshops on advanced VLSI systems, the testing and measurement thoery and practice related to these heterogeneous resources integrated into a SoC solution is a major unsolved problem that could greatly limit future advances.The advancements in process technologies provide for radically new types of devices, with commensurate design challenges and test and measurement needs. An example of such a system currently under development at the UW is a human/machine transducer chip-Universal Transducer Chip, a single integrated system capable of providing a speech recognition interface to a ubiquitous wireless network. Such a system is likely to become the standard interface modality for a wide range of new applications, from smart homes and smart test benches to ubiquitous high-performance computing fabrics. However, to achieve this potential, there are multiple test and measurement issues that must be addressed:o Radio frequency transceivers must be tested and characterized in the ISM (2.4GHz) and UNfl (5.6-5.8GHz) frequency bands for a broad range of emerging wireless standardso Low power, high performance wireless hardware implementations must be tested and measurement techniques must be developed and validated for future SoC applications in the LMDS bands at 17GHz, and aboveo Heterogeneous single-chip integration and test and measurement must be supported, allowing for the fabrication of RF, analog, high performance digital, and re-configurable subsystems within a single piece of siliconThe infrastructure contained in this proposal enables an investigation into the future of testing and measuring ultra-high-frequency SoC systems, years in advance of their commercialization. We will seek to develop and demonstrate a test and measurement methodology that can provide the benefits of multiple different resource types for numerous design domains. As an initial driver of these efforts, we will characterize a Human/Machine transducer chip, seeking to guide the development of future system-on-a-chip design and test methodologies. It is generally representative of future SoC systems that will operate at ever higher frequencies with ever-increasing levels of complexity. To support the design of such cutting-edge silicon systems, we will develop innovative techniques to handle numerous test issues:o Validation of techniques for integrating RF and Analog components into future ultra-low-voltage SoC designs.o Validation of high-performance, power efficient digital logic families for supporting these systems.o Integrated testing methodologies for complex, heterogeneous systems that can provide complete system test through an optimum combination of on-chip and off-chip ultra-high-frequency test environments.In addition to the development of new approaches for testing and measuring SoC chip designs, we will also develop innovative techniques for educating future high-frequency SoC designers. By providing an integrated curriculum including high-frequency test and measurement, along with a just-in-time learning environment, we will help create system architects capable of harnessing these radically new design techniques and opportunities.