Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Pipelined Data Converter Design Strategies for Sub-100nm Processes

模数转换器(ADC)是当今许多集成电路中所需的关键组件之一，随着应用范围的扩大和将大型系统集成到芯片上的能力成为现实，对ADC的应用和需求在未来十年中只会加速。与这一不断增长的需求并行并使其得以实现的是半导体技术的发展，其工艺的特征尺寸和电源电压不断缩小。虽然这些进展在大多数数字电路中提供了显著的速度和晶体管密度的提高，但它们对实现模拟和混合信号功能提出了越来越大的挑战，并且20年来使用相同的基本电路结构来实现关键功能块(如模数转换器)的策略在目前正在开发的亚100 nm工艺中将不再成功。本研究专注于开发可用于在亚100 nm半导体工艺中设计高性能模数转换器的设计方法，在亚100 nm半导体工艺中，不仅电源电压在下降，而且基本晶体管的增益特性也在恶化。该项目的三个主要举措是：a)开发能够在非常低的电源电压下工作的快速高增益运算放大器的技术；b)开发用于流水线数据转换器的内建自校准和内建自测试算法；c)将这些结果整合到将以高分辨率工艺制造的原型转换器中，以便可以通过实验验证理论性能特性。低电压运算放大器应该在低于100 nm的工艺中得到应用，远远超出其在流水线数据转换器中的使用范围。自校准策略基于将流水线数据转换器视为通过使用专用数字信号处理块来识别的系统。这种方法将提供成品率提高，并将固有地提供内建自测试的能力，随着日益复杂的模拟和混合信号功能深入嵌入大型单片系统中，内建自测试将变得越来越重要。

Analog to Digital Converters (ADCs) are one of the key components that are needed in many integrated circuits today and the application and demand for the converters will only accelerate throughout the next decade as applications expand and the ability to put large systems on a chip becomes reality. Paralleling and enabling this growing demand is an evolution in semiconductor technology with processes that have a continued shrinking of feature sizes and supply voltages. Although these evolutions are providing dramatic speed and transistor density improvements in most digital circuits, they are presenting increasing challenges for realizing analog and mixed-signal functions and the two decade-old strategy of using the same basic circuit structures to implement key functional blocks such as the analog to digital converter will no longer be successful in the sub-100nm processes that are now under development.This research is focused on developing design methodologies that can be used to design high-performance analog to digital converters in sub-100nm semiconductor processes in which not only the supply voltages are decreasing but also the gain characteristics of the basic transistor are deteriorating. The three major initiatives in the project are a) developing techniques for building fast high-gain operational amplifiers that can operate with very low supply voltages, b) developing built-in self-calibration and built-in self-test algorithms for pipelined data converters, and c) incorporating these results into a prototype converter than will be fabricated in a fine resolution process so that the theoretical performance characteristics can be experimentally validated.The low voltage operational amplifiers should find applications in sub-100nmprocesses well beyond their use in pipelined data converters. The self-calibration strategy is based upon treating the pipelined data converter as a system, which is identified through the use of a dedicated digital signal processing block. This approach will provide for yield enhancement and will inherently provide capability for built-in self-test which will be of increasing importance as increasingly complex analog and mixed-signal functions become deeply embedded in large single-chip systems.