Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Optimal Double-Gate MOSFET Structure for Mixed-signal Circuits

0120328KanThis proposal focuses on investigating innovative circuits based on double-gate MOSFET structures in the mixed signal environment.研究工作将建立一整套关于电路设计，器件建模，器件设计和器件制造的知识，以实现深亚微米双栅MOSFET技术的最佳性能和可靠操作。 从电路到制造的综合方面不仅可以提供对混合信号电路设计权衡的全面理解，而且还可以使参与该计划的研究生和本科生实现平衡发展。通过解析解和全二维静电求解器，对双栅MOSFET器件设计进行了初步的缩放研究。设计变量，如沟道长度，硅膜厚度，栅氧化层厚度，和接触功函数将根据不同的基准在电路应用中选择。两个通道之间的静态耦合可以被最大化或最小化，动态耦合可以被调谐以适应电路操作。通过对量子力学效应的适当设计考虑，可以实现包括DIBL（漏诱导势垒降低）考虑在内的陡峭亚阈值斜率。PI小组的新型肖特基S/D接触技术将在整个器件操作和电路要求中得到应用和评估。同时，随着双栅CMOS工艺的发展，基于类似结构的大型器件的实验测量，通过详细的模型化和尺度化研究，可以得到器件参数的预硅预测。 基于初步的解析解和数值解，我们将建立一个可扩展的双栅CMOS紧凑模型。预测的参数集和可扩展的器件模型将使混合信号电路设计的早期分析，这反过来又会给制造工艺权衡的方向。新型混合信号电路将使用紧密（无接触寄生）和快速（低至0.1ps，即，PI预计，这项任务将导致新的低压电路拓扑结构，利用双栅极MOSFET的两个栅极，以实现低功耗的高性能操作。他还希望确定大量有关如何针对不同电路应用优化双栅MOSFET结构的信息。创新主张可以通过使用拟议结构的两个栅极之间的紧密和快速耦合来获得新颖的混合信号电路功能。器件和电路协同设计的方法可以通过双栅MOSFET模拟和混合信号电路来演示。利用该器件独特的双栅结构，可以设计新型的低电压、低功耗、高性能的混合信号电路。

0120328KanThis proposal focuses on investigating innovative circuits based on double-gate MOSFET structures in the mixed-signal environment. The research efforts will establish a whole suite of knowledge on circuit design, device modeling, device design, and device fabrication for optimal performance and reliable operations in the deep submicron double-gate MOSFET technology. The comprehensive aspects from circuit to fabrication will not only provide a thorough understanding of the mixed-signal circuit design trade-off, but also will enable a balance development for graduate and undergraduate students participating in the program.Initial scaling studies on double-gate MOSFET device design has been performed by analytical solutions and the full-2D electrostatic solver. Design variables such as channel length, Si film thickness, gate oxide thickness, and contact work functions will be selected according to different benchmark in circuit applications. The static coupling between the two channels can be maximized or minimized, the dynamic coupling can be tuned to fit the circuit operations. Steep subthreshold slope including DIBL (drain-induced barrier lowering) consideration can be achieved through appropriate design consideration on quantum-mechanical effects. Novel Schottky S/D contact technology by the PI's group will be employed and evaluated in the overall device operations and circuit requirements. This modeling study will serve as the scaling guidelines for device and process design.Simultaneously with the fabrication process development of double-gate CMOS technology, pre-Si prediction of device parameters will be obtained from detailed modeling and scaling studies based on experimental measurement on the larger devices with similar structures. A scalable compact model for double-gate CMOS will be developed based on the preliminary analytical and numerical solutions. The predicted parameter set and the scalable device model will enable early analysis of mixed-signal circuit design, which will in turn give directives to fabrication process trade-off. Novel mixed-signal circuits will be constructed using the tight (no contact parasitic) and fast (down to 0.1ps, i.e., 10THz, limited by either the dielectric relaxation time or carrier transit time of carriers travelling between two channels) coupling between the two MOS structures.The PI expects that this task will result in new low-voltage circuit topologies that exploit both gates of the double-gate MOSFET to achieve high-performance operation with low power consumption. He also expects to determine a great deal about how the double-gate MOSFET structure can be optimized for different circuit applications.Innovative ClaimsNovel mixed-signal circuit functionality can be obtained from using the tight and fastcoupling between the two gates of the proposed structure.Methodology for device and circuit co-design can be demonstrated through double-gateMOSFET analog and mixed-signal circuits. Novel low-voltage, low-power mixed-signal circuits with high performance can be designed utilizing the unique double-gate structure of the proposed devices.