Collaborative Research: Platform-Based CAD for Power and Performance Optimization

由于集成电路芯片的设计变得越来越复杂，为了满足各种嵌入式计算产品的需求，预制平台芯片正变得越来越普遍。平台的趋势产生了对参数化计算架构的需求，这样平台的性能和功耗就可以适应不同产品的不同需求，并且可以针对特定产品的特定计算模式进行调优。这个项目将研究这种参数化的几个方面。它将演示对架构的内存组件进行广泛参数化的可行性，这些组件是影响功耗和性能的关键因素。它将定义构成面向平台的CAD的基本任务，在桌面和平台资源之间划分计算机辅助设计（CAD）任务，以产生快速、准确和经济有效的CAD解决方案，并为桌面/平台共同探索开发新的CAD探索算法。该研究将有利于平台设计师，他们需要了解参数和调整问题，以有效地构建高度参数化的平台及其相关的CAD工具，以及平台用户，他们可以利用这些平台和CAD工具开发比目前更有效的基于平台的设计。

As integrated circuit chips are becoming more complex to design, pre-fabricated platform chips, intended to meet the needs of a wide variety of embedded computing products, are becoming increasingly common. The trend towards platforms creates the need for parameterizing computing architectures such that platforms can have their performance and power consumption adapted to the different needs of different products, and that can be tuned to the particular compute patterns of a particular product. This project will investigate several aspects of such parameterization. It will demonstrate the feasibility of extensive parameterization of an architecture's memory components, key contributors to power and performance. It will define the basic tasks that make up platform-oriented CAD, partition computer-aided design (CAD) tasks between desktop and platform resources to yield fast yet accurate andcost-effective CAD solutions, and develop new CAD exploration algorithms for desktop/platform co-exploration. The research will benefit platform designers, who need an understanding of parameters and tuning issues to effectively build heavily parameterized platforms and their associated CAD tools, and platform users, who can utilize such platforms and CAD tools to develop more efficient platform-based designs than currently possible.