ITR: Dynamically Tunable Clustered Multithreaded Architectures

提出的研究目标是通过设计和评估动态可调集群多线程（DT-CMT）架构来有效地利用片上并行性。该架构结合了同步多线程架构（smt）的利用率优势和芯片多处理器（cmp）的速度优势。pi将设计一个架构，该架构可以快速配置到有限数量的组织中（从而最小化速度和密度影响），以平衡指令级并行性和线程级并行性，从而最大化利用率并最小化能量。这种方法的关键是开发软件系统（编译器、运行时系统、多路编程和多线程支持），分析应用程序需求，并将这些知识与硬件的反馈机制相结合。该方法的性能和节能潜力将通过仿真来表征。这个项目有可能对未来服务器和网络处理器的微架构和软件产生重大影响，并将有助于培养研究生设计未来越来越多的过程技术意识架构。拟议的工作将允许动态定制处理器架构，以满足日益多样化的应用需求，从而允许未来的处理器随着工艺技术的改进而扩展。

The goal of the proposed research is to efficiently exploit on-chip parallelism via the design and evaluation of a dynamically tunable clustered multithreaded (DT-CMT) architecture. The proposed architecture will combine the utilization advantages of simultaneous multithreaded architectures (SMTs) with the speed advantages of chip multiprocessors (CMPs). The PIs will design an architecture that can be rapidly configured into a restricted number of organizations (so as to minimize speed and density impact) in order to balance instruction-level parallelism and thread-level parallelism to maximize utilization and minimize energy. Key to this approach will be the development of software systems (compilers, runtime systems, multiprogramming and multithreaded support) that analyze application requirements and combine thisknowledge with feedback mechanisms from the hardware. The performance and power saving potential of this approach will be characterized via simulation.This project has the potential to significantly impact the microarchitecture and software of future server and network processors, and will help train the graduate students in the design of future increasingly process technology-aware architectures. The proposed work will allow dynamic tailoring of the processorarchitecture in order to meet the needs of increasingly diverse applications, thereby allowing future processors to scale as process technology improves.