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CAREER: Tools for Design for Manufacturability in Nanometer CMOS

CAREER: Tools for Design for Manufacturability in Nanometer CMOS
职业:纳米 CMOS 可制造性设计工具
批准号:
0347403
负责人:
Michael Orshansky
金额:
$40.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2004
资助国家:
美国
项目状态:
已结题
起止时间:
2004-08-15 至 2010-07-31

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中文摘要
翻译
提案编号:0347403INSTITUTION:U of Texas AustinPRINCIPAL调查员:Orshansky,MichaelTITLE:针对纳米CMOS可制造性设计的工具本研究的目标是开发模型、算法和概念性框架,以实现在纳米级CMOS技术中进行健壮的电路设计。大规模固态技术的制造和基本限制导致半导体器件物理特性的不可预测性增加。这项研究提出了一种新的设计范式,其中不确定性被计算机辅助设计工具明确地接受。这将通过统计建模、分析和优化的统一处理来实现。这项建议的具体目的是:(1)开发一个分析环境,以便及早评估工艺和器件变化对电路设计的影响。该工具将帮助就新设计和技术的特性做出高层决策。(2)开发一种准确、高效的统计静态时序分析算法,使电路设计者能够可靠地验证其设计的时序行为,并找到电路时序成品率的分布。(3)开发统计电路优化方法,以确定在频率、功率和成品率方面的最佳设计方案。这个项目的教育部分的目标是确保新一代工科学生对半导体物理和技术以及算法电路设计技术有全面的了解。为了实现这一目标,这项建议将:(1)开发两门新课程,强调固态技术、电路设计和计算机辅助设计算法的概念的联合处理;(2)通过直接外展和有针对性的本科生研究机会,积极招收代表性不足的学生;以及(3)促进行业专家积极参与教学。
英文摘要
PROPOSAL NO: 0347403INSTITUTION: U of Texas AustinPRINCIPAL INVESTIGATOR: Orshansky, MichaelTITLE: Tools for Design for Manufacturability in Nanometer CMOSThe goal of this research is to develop models, algorithms, and conceptual frameworks that will enable robust circuit design in nanometer scale CMOS technology. The manufacturing and fundamental limitations of scaled solid-state technology lead to increasing unpredictability in the physical properties of semiconductor devices. This research proposes a new design paradigm in which uncertainty is explicitly embraced by computer-aided design tools. This will be achieved via the unified treatment of statistical modeling, analysis, and optimization. This proposal specifically aims at: (1) Developing an analysis environment for early assessment of the impact of process and device variation on circuit design. The tool will assist in making high-level decisions on the properties of new designs and technologies. (2) Developing an accurate and efficient statistical static timing analysis algorithm which will allow circuit designers to reliably verify the timing behavior of their designs and find the distribution of circuit timing yield. (3) Developing statistical circuit optimization approaches that will enable identifying superior design alternatives with respect to frequency, power, and yield. The goal of the educational part of this program is to ensure that a new generation of engineering students has a comprehensive understanding of both the semiconductor physics and technology and the algorithmic circuit design techniques. To achieve that goal, this proposal will: (1) develop two new courses emphasizing joint treatment of concepts in solid-state technology, circuit design, and computer-aided design algorithms; (2) actively recruit underrepresented students through direct outreach and targeted research opportunities for undergraduates; and (3) promote active involvement of industrial experts in teaching.
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SHF: Medium: Simulation-Based Analysis of EM Side Channels in Embedded Systems: From Software to Fields
  • 批准号:
    1901446
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $120.0万
  • 财政年份:
    2019
  • 负责人:
    Michael Orshansky
  • 依托单位:
STARSS: Small: Simulation-Based Verification of EM Side-Channel Attack Resilience of Embedded Cryptographic Systems
  • 批准号:
    1527888
  • 项目类别:
    Standard Grant
  • 资助金额:
    $28.67万
  • 财政年份:
    2015
  • 负责人:
    Michael Orshansky
  • 依托单位:
SaTC: STARSS: Hardware Authentication through High-Capacity PUF-Based Secret Key Generation and Lattice Coding
  • 批准号:
    1441484
  • 项目类别:
    Standard Grant
  • 资助金额:
    $30.67万
  • 财政年份:
    2014
  • 负责人:
    Michael Orshansky
  • 依托单位:
A Hardware-Accelerated Transistor-to-Application SEU Simulation Platform
  • 批准号:
    1255757
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $18.3万
  • 财政年份:
    2013
  • 负责人:
    Michael Orshansky
  • 依托单位:
海外基金