EHS: Highly Flexible Multi-Mode Embedded Systems

摘要嵌入式系统设计的一个具有挑战性的方面是硬件/软件划分。许多系统任务可能是性能敏感的，但是所有这些任务的硬件实现可能过于昂贵。此外，对性能敏感但很少执行的任务的硬件实现导致低资源利用率。多模式系统已经成为这个问题的一个面积有效的解决方案，在一个单一的硬件空间中实现多个时间上互斥的性能敏感的任务。为了执行特定任务，硬件被配置为适当的模式。然而，现有的多模式技术具有有限的可重构性，因为只有数据路径互连可以改变，并且只能从模式到模式。本项目正在开发一种高度灵活的多模式嵌入式系统设计技术，使数据路径组件和控制结构以及互连的模式间和模式内重新配置。这种增加的灵活性导致在现有的多模式技术的显着的面积和功率节省。通过新的小规模可重构性（SSR）设计技术有效地获得硬件灵活性，该技术将少量的可重构逻辑和互连集成到主要固定的逻辑电路中，从而避免与通用可重构结构相关联的面积、延迟和功率损失。这些技术提供的设计范例需要重新评估嵌入式系统中的硬件/软件划分，因为与硬件实现相关的成本模型发生了重大变化。该项目包括三个主要组成部分。首先是多模式系统综合技术的发展，利用可重构数据路径组件和控制器提供的额外的硬件灵活性和内部模式可重构性。我们的目标是一个通用的系统综合算法框架（包括调度，分配和绑定算法），适用于各种嵌入式系统的应用。第二是SSR作为灵活的数据路径组件和控制器的硬件实现技术的发展。三是探讨了这种新的设计范式对嵌入式系统设计中软硬件划分的影响，

Lach - AbstractA challenging aspect of embedded system design is hardware/software partitioning. Many system tasks may be performance-sensitive, but hardware implementation of all such tasks may be prohibitively expensive. In addition, hardware implementation of tasks that are performance-sensitive but rarely executed results in low resource utilization. Multi-mode systems have emerged as an area-efficient solution to this problem, implementing multiple time-wise mutually exclusive performance-sensitive tasks in a single hardware space. To execute a particular task, the hardware is configured to the appropriate mode. However, existing multi-mode techniques have limited reconfigurability, as only the datapath interconnect can be changed and only from mode-to-mode.This project is developing a highly flexible multi-mode embedded system design technique that enables inter- and intra-mode reconfiguration of datapath components and control structures as well as interconnect. This added flexibility results in significant area and power savings over existing multi-mode techniques. The hardware flexibility is efficiently obtained via a new small-scale reconfigurability (SSR) design technique, which integrates small amounts of reconfigurable logic and interconnect into primarily fixed logic circuits, thus avoiding the area, delay, and power penalties associated with general-purpose reconfigurable fabric The design paradigm provided by these techniques requires a reevaluation of hardware/software partitioning in embedded systems, as the cost model associated with hardware implementation changes significantly.This project contains three primary components. First is the development of multi-mode system synthesis techniques that leverage the extra hardware flexibility provided by reconfigurable datapath components and controllers and intra-mode reconfigurability. The goal is a generic system synthesis algorithmic framework (including scheduling, allocation, and binding algorithms) that is applicable to a variety of embedded system applications. Second is the development of SSR as a hardware implementation technique for flexible datapath components and controllers. Third is exploring the effect this new design paradigm has on hardware/software partitioning in embedded system desig