CSR---SMA:Single-Chip Heterogeneous Multiprocessor Systems: Defining a New Level of Design

在过去的25年里，出现了一个价值50亿美元的行业，用于开发和支持用于集成电路(IC)的综合、验证和分析的工具和语言。在接下来的五年内，IC设计将进一步改变，因为在一个芯片上提供足够的晶体管用于大约100个16位处理器的数量级。这些系统的设计将通过利用任务级并行性来实现其性能目标。这些软件密集型系统需要的建模能力远远超出了传统的计算机辅助设计工具。虽然软件工程技术也可以作为设计辅助工具，但它们没有解决性能的重要方面；这是设计真实的、受约束的系统的关键目标。这些系统性能的核心是将并发任务调度到并发处理单元上。系统中某个点的瓶颈可能会导致系统范围的性能下降。本研究将致力于为单芯片异构型多处理系统的设计定义一个新的建模层次。该项目将调查基础模型的开发，包括处理资源、应用程序任务和调度程序，并将开发基于并发系统模型的诊断辅助工具，以及将在网站上提供的模拟器。这项研究将定义、演示和教授计算机系统建模的一个新层次。

A five billion dollar industry has arisen over the last 25 years to develop and support tools and languages for synthesis, verification, and analysis of integrated circuits (ICs). Within the next five years, IC design will further change as it will be possible to provide enough transistors on a single chip for on the order of a hundred 16-bit processors. The systems will be designed to meet their performance goals through the exploitation of task level parallelism. These software-intensive systems will require modeling capabilities far beyond traditional computer-aided design tools. While software engineering techniques also contribute as design aids, they do not address the important aspect of performance; a key goal in the design of real, constrained systems. Central to the performance of these systems is the scheduling of the concurrent tasks onto concurrent processing elements. Bottlenecks at one point in the system can cause system-wide performance degradations. This research will investigate defining a new level of modeling for the design of single-chip heterogeneous multiprocessing systems. The project will investigate the development of the underlying models that include processing resources, application tasks, and schedulers , and will develop a diagnostic aid based on the concurrent system model, and a simulator to be made available on a website. This research will define, demonstrate, and teach a new level of computer system modeling.