Investigation of Reliability-Constrained On-Chip Networks

可靠性约束的片上网络的研究在计算机架构师在未来十年及以后将面临的许多挑战中，对系统微架构功能域之间可靠的片上通信的需求日益增长。晶体管和布线资源的扩展和集成度的持续提高使得更多的系统功能可以在芯片上实现，但也带来了更多的电路缺陷和可变性。最近的趋势是以功能单元块、瓦片和处理器核心的形式将系统微架构划分为多个片上计算域，这减轻了芯片交叉延迟并促进了芯片生存性。也就是说，它有助于防止系统性能和成本受到深亚微米技术缩放的阻碍。随着这些发展，在用于互连计算域的片上网络中，对低延迟、高吞吐量和容错通信的支持变得越来越重要。最近的研究主要集中在片上网络的设计上，以满足一定的成本/性能目标（芯片面积，延迟和吞吐量），但很少有体系结构研究探讨特定于硬故障问题的片上网络可靠性问题，这被认为是一个日益严重的问题。在这项研究中，我们研究可靠性挑战和技术，随着技术扩展到深亚微米范围，芯片网络将满足制造产量和芯片可靠性目标。我们的目标是更充分地了解这个问题，并开发有效的资源和可靠性管理，故障隔离，动态重新配置和故障恢复，允许故障的微架构跨芯片分区，以提高可用性和延长寿命的芯片上的网络技术。我们努力提高对芯片故障机制的理解（其原因和影响）;适当地将其建模为与片上网络具体相关;开发方法和技术，（与用于芯片微体系结构的其他组件的技术合作）对硬故障有弹性;评价和评估拟议技术在预期工作量和常见操作条件下的效益;并且此外理解在使用所提出的故障恢复芯片上网络技术时的权衡，即，识别在给定存在其它可能约束的情况下可以最有效地应用各种技术的那些情况。 这项研究的学术价值是巨大的。这项研究是及时的，因为它解决了一个重要的问题，这个问题只会随着技术规模的不断进步而恶化。该研究将最终在以下方面做出关键贡献：（1）增加我们对最负责片上互连故障的基本设计，工艺和操作机制的理解，以及（2）产生用于提高片上互连可靠性和整体芯片可靠性的原创和有前途的技术。除了我们将通过该项目开发的模型和模拟环境产生的具体结果之外，这些工具工件可能会对未来的研究基础设施和教育产生深远的影响。它们将成为研究人员、学生和从业者了解、开发、评估和权衡先进技术和系统所需的替代可靠性技术的宝贵资产。我们开发的工具将公开提供，预计将得到广泛使用。这项研究的结果也将通过出版物广泛传播。这项研究的广泛影响是重大和深远的。这项研究可能对不久的将来纳米技术（分子，量子等）的成功产生深远的影响。用于实现CMOS时代之后的集成电路，因为预期在这些技术中实现的IC具有比CMOS IC实质上更多的硬故障（数量级）。可靠性技术，如那些将来自这项研究将是至关重要的系统中实现这些技术，以及那些在未来的深亚微米技术。从近期来看，这项研究中的许多想法可能会转移到系统级网络中，其中的形状因子约束通常不像片上那样严格。

Abstract0541417Alexander SawchukLos Angeles, CAInvestigation of Reliability - Constrained On-Chip NetworksAmong the many challenges computer architects will face over the next decade and beyond is the growing demand for reliable on-chip communication between system microarchitecture functional domains. Continued increases in scaling and integration of transistor and wiring resources are allowing more system functions to be implemented on chip, but also more circuit defects and variability. Recent trends toward partitioning the system microarchitecture into multiple on-chip compute domains in the form of functional unit blocks, tiles and processor cores mitigate chipcrossing delays and facilitate chip survivability. That is, it helps to prevent system performance and cost from being encumbered by deep submicron technology scaling. With these developments, support for low latency, high throughput, and fault tolerant communication is becoming more and more critical within the on-chip network used to interconnect the compute domains. Much recent research is directed toward the design of on-chip networks to meet certain cost/performance goals(chip area, latency and throughput), but very little architecture research explores on-chip networkreliability issues specific to the problem of hard faults, which is recognized as a growing problem.In this research, we investigate reliability challenges and techniques for on-chip networks that will meet manufacturing yield and chip reliability targets as technology scales into the deep submicron regime. The goal is to understand the problem more fully and to develop on-chip network techniques for efficient resource and reliability management, fault isolation, dynamic reconfiguration and fault recovery to allow fault-stricken microarchitectures partitioned across a chip to have increased usability and prolonged life. We endeavor to increase understanding of chip failure mechanisms (their causes and impact); appropriately model them as related specifically to on-chip networks; develop approaches and techniques that will allow on-chip networks (in cooperation with techniques for other components of the chip microarchitecture) to be resilient tohard faults; evaluate and assess the benefit of the proposed techniques under expected workloads and common-case operational conditions; and, furthermore, understand the tradeoffs in using the proposed fault-resilient on-chip network techniques that is, identify those situations in which various techniques can be most usefully applied given the existence of other possible constraints. The Intellectual Merit of this research is substantial. The research is timely as it addresses an important issue that will only worsen with continuing advancements in technology scaling. The research will culminate with key contributions made in (1) increasing our understanding of the fundamental design, process, and operational mechanisms most responsible for on-chip interconnect failures and (2) producing original and promising techniques for increasing on-chip interconnect reliability and chip reliability as a whole. Beyond the specific results produced by the models and simulation environments we will develop through this project, these tool artifacts will likely have a profound impact on future research infrastructure and education for years to come. Theywill be invaluable assets to researchers, students, and practitioners for understanding, developing,evaluating, and trading-off alternative reliability techniques as demanded by advanced technologies and systems. The tools we develop will be made publicly available and are expected to have widespread use. The results of this research will also be widely disseminated through publications. The Broader Impact of this research is significant and far-reaching. This research can have a profound impact on the success of near-future nanoscale technologies (molecular, quantum, etc.) used to implement integrated circuits beyond the CMOS era as ICs implemented in these technologies are expected to have substantially more hard faults (orders of magnitude) than CMOS ICs. Reliability techniques such as the ones that will be derived from this research will be critical to systems implemented in these technologies as well as those implemented in future deep submicron technology. In the nearer term, many of the ideas coming from this research may be transferrable to system-level networks, where form-factor constraints often are not as rigid as they are on-chip.