SHF: Small: Collaborative Research: Design of Many-core NoCs for the Dark Silicon Era

各种形式和规模的计算系统的激增极大地促进了科学、技术、发现和整个社会的发展，造福于人类。作为当前和未来计算系统的关键组成部分？包括物联网，众核芯片多处理器（CMP）正面临由Dennard缩放的限制带来的前所未有的功率挑战。这就需要将众核芯片设计成具有降低片上资源的能力，以有效地提供可扩展的性能，同时保持功耗和能耗与计算负载成比例。这种必要性导致相当一部分众核芯片必须变暗，从而迎来了暗硅时代。为了促进暗硅计算，不仅计算资源（即，处理器核）而且还包括通信资源（即，本研究探讨了在片上网络（NoC）架构中利用暗硅技术的新机遇、重大挑战和创新解决方案，以满足暗硅时代对性能、功耗和能源的要求。目标是使得非必要的NoC路由器能够在需要时被断电，以及使得对应的最大数量的路由器和路由器组件能够被断电，以用于通电的处理器核的数量的给定减少，以便提供能量成比例的、低功率的片上通信。在探索的一些具体研究领域中，有替代拓扑结构和协调路由算法，以实现NoC路由器的更有效的功率门控，用于利用NoC与其他片上系统组件之间的协调的整体方法，以及考虑关键应用特性，以及新颖的面向分组的动态功率控制方案，其探索超出常规目标低负载业务区域的节能机会。除了其技术贡献可以影响暗硅计算的根本进步之外，这项研究还对研究教育和推广产生了更广泛的影响。这项研究的结果被纳入研究生课程，课程和本科生的研究经验。此外，还开展了推广活动，以扩大来自不同背景和发展水平的人对计算的参与。

The proliferation of computing systems of various forms and scales have significantly advanced science, technology, discovery and society at large for the benefit of human kind. As the key building blocks of current and future computing systems?including the Internet of Things, many-core chip multiprocessors (CMPs) are facing unprecedented power challenges brought on by limits in Dennard scaling. This necessitates many-core chips to be designed with the ability to power down on-chip resources to effectively provide scalable performance while keeping power and energy consumption proportional to computing load. This necessity leads to considerable portions of many-core chips having to go dark, thus ushering in the era of dark silicon. To facilitate dark silicon computing, not only computational resources (i.e., processor cores) but also communication resources (i.e., networks on chips, or NoCs) used to connect the computational resources must be developed that can be powered up or down proportionally with performance scalability in response to prevailing load.This research investigates new opportunities, significant challenges, and innovative solutions for harnessing dark silicon in NoC architectures that meet performance, power and energy requirements in the dark silicon era. The objective is to enable non-essential NoC routers to be powered down when needed as well as to enable a corresponding maximum number of routers and router components to be powered down for a given reduction in the number of powered-up processor cores in order to provide energy-proportional, low-power, on-chip communication. Among some of the specific lines of research that are explored are alternative topologies and coordinated routing algorithms to enable more efficient power-gating of NoC routers, holistic approaches for exploiting coordination between the NoC and other on-chip system components as well as factoring in key application characteristics, and novel packet-oriented dynamic power control schemes that explore energy-saving opportunities beyond the conventionally targeted low-load traffic region. Beyond its technical contributions that can impact fundamental advancement in dark silicon computing, this research also has impact more broadly on research education and outreach. Findings from this research are incorporated into graduate curriculum, courses, and undergraduate research experiences. Outreach activities to broaden participation in computing of persons from diverse backgrounds and development levels are also featured.