SHF: Small: Collaborative Research: Design of Many-core NoCs for the Dark Silicon Era

各种形式和规模的计算系统的激增极大地促进了科学、技术、发现和整个社会的进步，造福于人类。作为当前和未来计算系统(包括物联网)的关键构建块，多核芯片多处理器(CMP)正面临着因Dennard规模限制而带来的前所未有的功耗挑战。这就要求多核芯片的设计必须能够关闭片上资源，以有效地提供可扩展的性能，同时保持功耗和能源消耗与计算负载成正比。这种必要性导致相当一部分多核芯片不得不变暗，从而开启了暗硅时代。为了促进暗硅计算，不仅需要开发计算资源(即处理器核)，还必须开发用于连接计算资源的通信资源(即片上网络或片上网络)，这些资源可以根据当前的负载按比例加电或按性能扩展。本研究旨在研究在暗硅时代满足性能、功率和能量要求的片上系统架构中利用暗硅的新机会、重大挑战和创新解决方案。其目的是在需要时能够使非必要的NOC路由器断电，并且能够在通电的处理器核心的数量的给定减少的情况下使相应的最大数目的路由器和路由器组件断电，以便提供能量成比例的低功率片上通信。在所探索的一些特定研究线路中，有用于实现更有效的NOC路由器功率选通的替代拓扑和协调的路由算法、用于利用NOC和其他片上系统组件之间的协调以及考虑关键应用特性的整体方法、以及探索传统目标低负载业务区域之外的节能机会的新颖的面向分组的动态功率控制方案。除了它的技术贡献可以影响暗硅计算的根本进步之外，这项研究还对研究教育和推广产生了更广泛的影响。这项研究的结果被纳入研究生课程、课程和本科生研究经验。还开展了外联活动，以扩大来自不同背景和发展水平的人对计算机的参与。

The proliferation of computing systems of various forms and scales have significantly advanced science, technology, discovery and society at large for the benefit of human kind. As the key building blocks of current and future computing systems?including the Internet of Things, many-core chip multiprocessors (CMPs) are facing unprecedented power challenges brought on by limits in Dennard scaling. This necessitates many-core chips to be designed with the ability to power down on-chip resources to effectively provide scalable performance while keeping power and energy consumption proportional to computing load. This necessity leads to considerable portions of many-core chips having to go dark, thus ushering in the era of dark silicon. To facilitate dark silicon computing, not only computational resources (i.e., processor cores) but also communication resources (i.e., networks on chips, or NoCs) used to connect the computational resources must be developed that can be powered up or down proportionally with performance scalability in response to prevailing load.This research investigates new opportunities, significant challenges, and innovative solutions for harnessing dark silicon in NoC architectures that meet performance, power and energy requirements in the dark silicon era. The objective is to enable non-essential NoC routers to be powered down when needed as well as to enable a corresponding maximum number of routers and router components to be powered down for a given reduction in the number of powered-up processor cores in order to provide energy-proportional, low-power, on-chip communication. Among some of the specific lines of research that are explored are alternative topologies and coordinated routing algorithms to enable more efficient power-gating of NoC routers, holistic approaches for exploiting coordination between the NoC and other on-chip system components as well as factoring in key application characteristics, and novel packet-oriented dynamic power control schemes that explore energy-saving opportunities beyond the conventionally targeted low-load traffic region. Beyond its technical contributions that can impact fundamental advancement in dark silicon computing, this research also has impact more broadly on research education and outreach. Findings from this research are incorporated into graduate curriculum, courses, and undergraduate research experiences. Outreach activities to broaden participation in computing of persons from diverse backgrounds and development levels are also featured.