SHF: Small: Collaborative Research: Design of Many-core NoCs for the Dark Silicon Era

各种形式和规模的计算机系统的激增极大地推动了科学、技术、发现和整个社会的发展，造福于人类。作为当前和未来计算系统的关键组成部分？包括物联网在内的多核芯片多处理器（cmp）正面临着登纳德缩放限制带来的前所未有的功耗挑战。这就要求在设计多核芯片时能够降低片上资源的功耗，从而有效地提供可扩展的性能，同时保持功耗和能耗与计算负载成比例。这种需求导致相当一部分多核芯片不得不变暗，从而迎来了暗硅时代。为了促进暗硅计算，不仅要开发计算资源（即处理器内核），还要开发用于连接计算资源的通信资源（即芯片上的网络或noc），这些资源可以根据当前负载的性能可伸缩性按比例上电或下电。本研究探讨了在NoC架构中利用暗硅的新机遇、重大挑战和创新解决方案，以满足暗硅时代的性能、功率和能源需求。我们的目标是在需要时关闭非必要的NoC路由器，并在给定的上电处理器内核数量减少的情况下，使相应的最大数量的路由器和路由器组件关闭电源，以提供能量比例、低功耗、片上通信。在一些特定的研究方向中，探索了替代拓扑和协调路由算法，以实现更有效的NoC路由器功率门控，利用NoC与其他片上系统组件之间的协调以及考虑关键应用特性的整体方法，以及新颖的面向分组的动态功率控制方案，以探索超越传统目标低负载流量区域的节能机会。除了对暗硅计算的基础性进步做出技术贡献外，这项研究还对研究教育和推广产生了更广泛的影响。这项研究的结果被纳入研究生课程、课程和本科生的研究经历。此外，还举办了外联活动，以扩大来自不同背景和发展水平的人对计算机的参与。

The proliferation of computing systems of various forms and scales have significantly advanced science, technology, discovery and society at large for the benefit of human kind. As the key building blocks of current and future computing systems?including the Internet of Things, many-core chip multiprocessors (CMPs) are facing unprecedented power challenges brought on by limits in Dennard scaling. This necessitates many-core chips to be designed with the ability to power down on-chip resources to effectively provide scalable performance while keeping power and energy consumption proportional to computing load. This necessity leads to considerable portions of many-core chips having to go dark, thus ushering in the era of dark silicon. To facilitate dark silicon computing, not only computational resources (i.e., processor cores) but also communication resources (i.e., networks on chips, or NoCs) used to connect the computational resources must be developed that can be powered up or down proportionally with performance scalability in response to prevailing load.This research investigates new opportunities, significant challenges, and innovative solutions for harnessing dark silicon in NoC architectures that meet performance, power and energy requirements in the dark silicon era. The objective is to enable non-essential NoC routers to be powered down when needed as well as to enable a corresponding maximum number of routers and router components to be powered down for a given reduction in the number of powered-up processor cores in order to provide energy-proportional, low-power, on-chip communication. Among some of the specific lines of research that are explored are alternative topologies and coordinated routing algorithms to enable more efficient power-gating of NoC routers, holistic approaches for exploiting coordination between the NoC and other on-chip system components as well as factoring in key application characteristics, and novel packet-oriented dynamic power control schemes that explore energy-saving opportunities beyond the conventionally targeted low-load traffic region. Beyond its technical contributions that can impact fundamental advancement in dark silicon computing, this research also has impact more broadly on research education and outreach. Findings from this research are incorporated into graduate curriculum, courses, and undergraduate research experiences. Outreach activities to broaden participation in computing of persons from diverse backgrounds and development levels are also featured.