SHF: Small: Enhancing Power, Performance, and Resource Efficiency of Many-core NoCs

SHF：小型：增强多核 NoC 的功耗、性能和资源效率

• 批准号: 1321131
• 负责人: Timothy Pinkston
• 金额: $ 50万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-07-01 至 2018-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1321131&HistoricalAwards=false
• 关键词: SHF; Small; Enhancing; Power; Performance

Continued advancement of computing is of critical importance given the ubiquitous use of computing systems in various forms across a growing landscape-from implantable and wearable biomedical devices to facilitate personalized healthcare; to embedded and smart-sensor devices to facilitate efficient transportation and civil infrastructure; to cloud servers to facilitate data collection, mining, modeling and discovery; to many other scientific, economic, and social computing applications touching numerous disciplines and sectors. Unrelenting progress in semiconductor technologies and continual emergence of new application areas spur unprecedented development of many-core chip multiprocessors (CMPs) to satisfy increasing performance expectations and tightening power and resource constraints of future systems. Along with this parallel processing paradigm comes many challenges for efficiently interconnecting tens to hundreds of cores on a chip and possibly many thousands of chips in stand-alone or distributed systems. To meet the challenges, on-chip network (or NoC) communication architectures must be developed that provide scalable performance while both requiring minimal resources and consuming ultra-low power. This research investigates cross-cutting approaches and techniques to enhance on-chip network power, performance, and resource efficiency in CMP systems. Architecture-level support is explored for effectively exploiting circuit-level power-gating techniques. The objective is to maximize static power savings and minimize performance penalty of the NoC while conserving overall system dynamic power and energy expenditure when applying the techniques. Innovative approaches for minimizing NoC resources and enabling flexibility in resource utilization are also explored. The objective is to improve NoC resource efficiency while balancing system-level tradeoffs. The research plan establishes a systematic, comprehensive, and empirically-based method of investigating efficient communication architectures for many-core CMP systems, soundly grounded by theoretical support, that will lead to the design of promising new approaches and techniques. Beyond its contribution to fundamental advancements in computing, this research has broader potential impact to society through its outreach activities to broaden participation in computing and workforce development of persons from diverse backgrounds.

鉴于计算系统以各种形式在不断发展的领域中无处不在——从可植入和可穿戴生物医学设备到促进个性化医疗保健，计算的持续进步至关重要；嵌入式和智能传感器设备，以促进高效的交通和民用基础设施；到云服务器以促进数据收集、挖掘、建模和发现；涉及许多学科和领域的许多其他科学、经济和社会计算应用程序。半导体技术的不断进步和新应用领域的不断出现，刺激了多核芯片多处理器（CMP）的空前发展，以满足日益增长的性能期望以及未来系统日益严格的功率和资源限制。伴随这种并行处理范例而来的是如何有效地互连芯片上的数十到数百个内核以及独立或分布式系统中的数千个芯片的许多挑战。为了应对这些挑战，必须开发片上网络（或 NoC）通信架构，以提供可扩展的性能，同时需要最少的资源和超低功耗。这项研究研究了增强 CMP 系统中片上网络功耗、性能和资源效率的跨领域方法和技术。探索了架构级支持以有效利用电路级功率门控技术。目标是在应用这些技术时最大限度地节省静态功耗并最大限度地减少片上网络的性能损失，同时节省整个系统的动态功耗和能源消耗。 还探讨了最大限度地减少片上网络资源并实现资源利用灵活性的创新方法。目标是提高片上网络资源效率，同时平衡系统级权衡。 该研究计划建立了一种系统的、全面的、基于经验的方法来研究多核 CMP 系统的高效通信架构，该方法有坚实的理论支持，这将导致设计有前景的新方法和技术。除了对计算领域的根本性进步做出贡献之外，这项研究还通过其扩大不同背景人员对计算和劳动力发展的参与的外展活动，对社会产生了更广泛的潜在影响。