SHF: Small: Enhancing Power, Performance, and Resource Efficiency of Many-core NoCs

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Continued advancement of computing is of critical importance given the ubiquitous use of computing systems in various forms across a growing landscape-from implantable and wearable biomedical devices to facilitate personalized healthcare; to embedded and smart-sensor devices to facilitate efficient transportation and civil infrastructure; to cloud servers to facilitate data collection, mining, modeling and discovery; to many other scientific, economic, and social computing applications touching numerous disciplines and sectors. Unrelenting progress in semiconductor technologies and continual emergence of new application areas spur unprecedented development of many-core chip multiprocessors (CMPs) to satisfy increasing performance expectations and tightening power and resource constraints of future systems. Along with this parallel processing paradigm comes many challenges for efficiently interconnecting tens to hundreds of cores on a chip and possibly many thousands of chips in stand-alone or distributed systems. To meet the challenges, on-chip network (or NoC) communication architectures must be developed that provide scalable performance while both requiring minimal resources and consuming ultra-low power. This research investigates cross-cutting approaches and techniques to enhance on-chip network power, performance, and resource efficiency in CMP systems. Architecture-level support is explored for effectively exploiting circuit-level power-gating techniques. The objective is to maximize static power savings and minimize performance penalty of the NoC while conserving overall system dynamic power and energy expenditure when applying the techniques. Innovative approaches for minimizing NoC resources and enabling flexibility in resource utilization are also explored. The objective is to improve NoC resource efficiency while balancing system-level tradeoffs. The research plan establishes a systematic, comprehensive, and empirically-based method of investigating efficient communication architectures for many-core CMP systems, soundly grounded by theoretical support, that will lead to the design of promising new approaches and techniques. Beyond its contribution to fundamental advancements in computing, this research has broader potential impact to society through its outreach activities to broaden participation in computing and workforce development of persons from diverse backgrounds.