Sequentially Transparent Synthesis
Sequentially Transparent Synthesis
批准号:
0702668
负责人:
Robert Brayton
金额:
$0.0万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2007
资助国家:
美国
项目状态:
已结题
起止时间:
2007-07-01 至 2010-06-30
中文摘要
ID:CCF-0702668项目标题:顺序透明合成PI名称:Brayton,Robert K.机构:加州大学伯克利分校摘要:微电子设备已经渗透到我们的日常生活中,从计算机到视频游戏。这些设备的高效制造是该国技术竞争力的关键,并意味着设计过程的自动化。因此,需要研究和不断开发能够表示、优化和实现复杂数字系统的计算机辅助设计(CAD)软件。这是一项艰巨的任务,如果不进行持续的研究,CAD软件的开发将跟不上对新数字电子系统设计能力、种类和速度的日益增长的需求。拟议的工作集中在正在设计的电子系统的功能描述自动生成和转换的关键领域的基础研究。我们的目标是优化,以根据设计需求而变化的标准为目标,例如优化最低功耗,这对手机等便携设备以及为互联网提供动力的大量计算服务器非常重要。这项研究的一个主要焦点是一个称为顺序综合和验证的领域。大多数数字系统可以抽象地看作有限状态机(FSM)。大多数优化FSM的CAD算法通过忽略内存组件(称为组合优化)来处理非常有限的FSM视图。这导致了非常不理想的结果。操作内存的优化(顺序优化)通常被忽略,因为它们不能扩展到大型系统,并且很难验证结果的正确性。(1)提出了一种新的有限状态机功能表示法,使顺序优化和验证变得更容易;(2)统一了几个以前不相关的优化目标,从而可以在更短的时间内找到更好的解决方案。该项目成功完成后,将为新一代高效CAD软件的研发做出贡献。它将提高设计人员的工作效率,降低开发成本,并缩短复杂系统的设计、实施和验证的上市时间。
英文摘要
ID: CCF-0702668Project Title: Sequentially Transparent SynthesisPI name: Brayton, Robert K. Institution: University of California-BerkeleyAbstract:Microelectronic devices are already pervasive in our everyday life, from computers to video games. Efficient manufacturing of these devices is key to this country's technology competitiveness and implies automating the design process. Thus, computer-aided design (CAD) software, capable of representing, optimizing, and implementing complex digital systems needs to be researched and continually developed. This is a demanding task and without continual research, development of CAD software will not keep up with the growing demands on the capacity, variety, and speed of designing new digital electronic systems.The proposed work focuses on basic research in the key area of automatically creating and transforming functional descriptions of electronic systems that are being designed. The goal is optimization, targeting criteria that vary depending on the design needs, e.g. optimizing for minimal power consumption, which is important for portable devices, such as cell phones, as well the huge banks of compute servers that power the internet. A primary focus of this research is in an area called sequential synthesis and verification. Most digital systems can be viewed abstractly as finite state machines (FSMs). Most CAD algorithms, which optimize these, work on a very limited view of FSMs by ignoring the memory components (called combinational optimization). This leads to very suboptimal results. Optimizations, which manipulate the memory (sequential optimization) are usually ignored because they are not scalable to large systems, and it is too hard to verify the correctness of the result. The research to be performed (1) advocates a novel representation of FSM functionality that makes sequential optimization and validation easier and (2) unifies several previously unrelated optimization goals, which allows for finding better solutions in shorter time.The project, when successfully completed, will contribute to the research and development of a new generation of efficient CAD software. It will boost designer productivity, lower development costs, and shorten the time to market for the design, implementation, and verification of complex systems.
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专著(0)
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会议论文
SHF: Small: Bit-level Formal Verification: Keeping Pace with Industrial Needs
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批准号:1219154
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项目类别:Standard Grant
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资助金额:$45.0万
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财政年份:2012
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负责人:Robert Brayton
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依托单位:
ITR: Synthesis System for Discrete Event Systems through Solving Equations over Mathematical Machines
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批准号:0312676
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项目类别:Continuing Grant
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资助金额:$30.0万
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财政年份:2003
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负责人:Robert Brayton
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依托单位:
海外基金