SBIR Phase II: VLSI Clocking Using BDS Technology

这个SBIR第二阶段研究项目旨在展示一种独特的电路方法，用于在CMOS芯片中分配GHz时钟，该方法提供最先进的性能，并且是模块化的、可扩展的和可重用的。该技术的理论基础是在片上传输线上实现的双向信令(BDS)原理。该项目包括综合测试芯片的设计、制造和评估，旨在验证这种新方法的关键方面，如长距离配电系统的实用精度、廉价高质量集成传输线的实现以及用于本地时钟产生的低功耗高精度有源电路的设计。如果实验室测试证实了预期的性能和特点，这种方法将成为一种有价值的超大规模集成电路(VLSI)新技术的基础。时钟分配的可扩展和可重复使用的电路知识产权(IP)的展示将使VLSI设计方法得到重大简化，给集成电路制造商带来巨大的好处。半导体行业将能够为计算机和通信设备等系统生产更快的处理、更低的功耗和更低的成本的VLSI组件。

This SBIR Phase II research project intends to demonstrate a unique circuit method for GHz clock distribution inside CMOS chips, which provides state-of-the-art performance and is modular, scalable, and reusable. The theoretical foundation of this technology is the Bi-Directional Signaling (BDS) principle implemented over on-chip transmission lines. The project covers the design, fabrication, and evaluation of a comprehensive test chip aimed at validating key aspects of this new method such as the practical accuracy of a long distribution system, the realization of inexpensive high-quality integrated transmission lines, and the design of low power high precision active circuits for local clock generation. If laboratory tests confirm the expected performance and features, this method will be the basis of a valuable new VLSI Very Large Scale Integration (VLSI) technology.The demonstration of scalable and reusable circuit Intellectual Property (IP) for clock distribution will cause a major simplification in the VLSI design methodology with substantial benefits to the manufacturers of integrated circuits. The semiconductor industry will be able to produce faster processing, lower power, and lower cost VLSI components for systems such as computers and communication devices.