CAREER: Reliable On-Chip Wireless Communication Network for Multi-Core Systems

多核处理平台的应用日益广泛。从消费类多媒体到图像处理再到国防应用，包含大量嵌入式内核的新设计不断涌现。片上网络(NoC)是一种能够在单个芯片中集成大量嵌入式内核的技术。传统的片上网络虽然具有诸多优点，但其基于平面金属互连的多跳通信存在严重的性能限制，其中两个相距较远的块之间的数据传输会导致较高的延迟和能量消耗。如果NoC中的所有或部分有线链路被高带宽单跳无线信道取代，这些问题可以同时解决。此外，无线链路将缓解NoC中的线路拥塞问题。最近的研究发现，良好的发射和吸收特性导致碳纳米管(CNT)具有类似天线的行为。这为详细研究使用碳纳米管天线构建无线NoC(WiNoC)的可能性提供了新的机会，并随后使WiNoC能够稳健地应对纳米设备固有的性能不确定性。S的总体研究目标将通过追求两个具体目标来实现：1)建立WiNoC架构的设计权衡和性能评估；所建议的WiNoC具有超越相应有线架构的能力；2)应用差错控制码使WiNoC对可能的故障具有健壮性；通过采用高效的信道编码方案，使WiNoC对各种类型的故障具有健壮性。这里提出的研究意义重大，因为它从一个全新的角度解决了芯片上的互连问题，即通过开发纳米级的无线网络，而不是追求相对传统的有线互连方法的渐进式改进。通过将无线电通信世界带入片上环境，所提出的研究具有改变多核芯片设计的能力。该提案的教育目标是招收和留住本科生、高中生和工程专业中代表性不足群体的学生。接触研究将伴随着积极的促进活动，包括对工程学的广泛介绍和个性化援助，以增加目标学生的学术准备。教育活动预计将增加皮涅狄格系学生的研究和教育机会。这类学生的进步预计将产生广泛的社会影响。该奖项由2009年《美国复苏和再投资法案》(公法111-5)资助。

Multi-core processing platforms have an increasingly broad range of applications. From consumer multimedia to image processing to defense applications, new designs containing large numbers of embedded cores are emerging. Network-on-Chip (NoC) has emerged as an enabling technology to integrate large numbers of embedded cores in a single die. In spite of all its advantages, a serious performance limitation in a traditional NoC arises from its planar metal interconnect-based multi-hop communication, wherein the data transfer between two distant blocks gives rise to high latency and energy dissipation. These problems can be simultaneously resolved if all or some of the wired links in a NoC are replaced by high-bandwidth single-hop wireless channels. Moreover, wireless links will alleviate the problem of wire congestion in NoCs.Recent research has uncovered excellent emission and absorption characteristics leading to antenna-like behavior in carbon nanotubes (CNTs). This opens up new opportunities for detailed investigations regarding the possibility of building a wireless NoC (WiNoC) with CNT antennas and subsequently making the WiNoC robust against performance uncertainties inherent in nanodevices. The CAREER proposal?s overall research objective will be attained by pursuing two specific goals: 1) Establish design trade-offs and evaluate performance of WiNoC architectures; the proposed WiNoC has the capability to outperform corresponding wireline architectures; 2) Apply error control codes to make the WiNoC robust against possible malfunctions; by incorporating efficient channel coding schemes, the WiNoC will be made robust against varied types of malfunctions. The research proposed here is significant, as it addresses the on-chip interconnect problem from a fundamentally new perspective, namely by developing a wireless network at the nanoscale, as opposed to pursuing incremental improvements of relatively traditional methods of wire-line interconnection. By bringing the world of radio communication to the on-chip environment, the proposed research has the capability to transform the design of multi-core chips. The educational objective of the proposal is to recruit and retain undergraduates, high school students and students from the underrepresented groups in the engineering program. Exposure to research will be accompanied by proactive enabling activities, including broad spectrum introduction to engineering and individualized assistance to increase academic preparedness of the targeted students. The educational activities are expected to enhance research and educational opportunities for underrepresented students in the PI?s department. Advancement of such students is expected to have broad societal impact.This award is funded under the American Recovery and Reinvestment Act of 2009(Public Law 111-5).