CAREER: Wireless Network-on-Chip: A New Communication Paradigm for Heterogeneous Gigascale MPSoCs

提案ID：0845983标题：Career：Wireless Network-on-Chip：适用于不同千兆级MPSoCsPI的新通信范例名称：赵，Danella研究所：路易斯安那大学拉斐特分校ABSTRACT许多核心系统芯片(MCSoC)设计正在迅速涌现，其中数百甚至数千个IP核心集成在一个芯片上。此类MCSoC器件可实现卓越的性能提升，同时避开时钟频率调节的功率和散热限制。因此，片上通信结构成为性能的决定因素。该项目旨在开发一种新的片上通信系统，称为无线片上网络(WNoC)，以支持下一代千兆级异构MCSoC计算性能的指数增长。PI从多个关键方面阐述了WNoC的研究方向。开发超宽带物理层，实现高数据速率、高带宽、低功耗的无线片上通信。系统架构将以通信和计算分离的方式设计，并将开发可重新配置的射频基础设施，以解决MCSoC的异构性。分层协议将专门设计，以解决WNoC与传统无线网络的不同特征，并简化硬件实施。高度紧凑和可配置的射频节点将被设计为支持不同的架构和针对特定应用映射的定制。将开展一系列开发和原型活动，以证明WNoC的适用性和可行性。在即将到来的纳米级MCSoC范例中，用于高性能计算的芯片内RF/无线互连网络领域可能会有一些突破。边界影响：该项目将对正在进行的和未来的高性能计算纳米器件研究产生非常广泛的影响。将探索课堂教学的创新教学方法。将为少数族裔和女性学生提供研究机会。它将促进与行业和政府实验室的伙伴关系。

Proposal ID: 0845983 Title: CAREER: Wireless Network-on-Chip: A New Communication Paradigm for Heterogeneous Gigascale MPSoCsPI name: Zhao, Danella Institution: University of Louisiana at Lafayette ABSTRACTMany-core System-on-Chip (MCSoC) designs are rapidly emerging, where hundreds or even thousands of IP cores are integrated on a single die. Such MCSoC devices allow superior performance gains while side-stepping the power and heat dissipation limitations of clock frequency scaling. Consequently, the on-chip communication fabric becomes the performance determinant. This project aims at developing a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC) to sustain the exponential growth of computing performance in the next generation gigascale heterogeneous MCSoCs. The PI lays out the research directions of WNoC from various crucial aspects. The UWB physical layer will be explored to accomplish high data-rate, high bandwidth and low-power wireless on-chip communication. The system architecture will be designed in a way that decouples communication from computation, and a reconfigurable RF infrastructure will be developed to address the heterogeneity of MCSoC. The layered protocol will be specially designed to tackle distinct features of WNoC from conventional wireless networks and to simplify the hardware implementation. Highly compact and configurable RF nodes will be designed to support heterogeneous architecture and customization for specific application mapping. A suite of development and prototyping activities will be carried out to demonstrate the applicability and feasibility of WNoC. Some breakthroughs could be forthcoming in the area of intra-chip RF/wireless interconnect network for high performance computing in the upcoming nanoscale MCSoC paradigm. Boarder Impact: This project will have a very broad impact on the on-going and future research in Nanodevices for high performance computation. Innovative pedagogical methods for classroom instruction will be explored. Research opportunities will be offered for minority and female students. It will foster the partnerships with industry and government laboratories.