TC: Medium: Collaborative Research: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer Protection

摘要：集成多层保护的防侧信道嵌入式处理器嵌入式数字系统无处不在，其中可能包含敏感信息，如果落入坏人之手，可能被用于恶意目的。因此，在这些设备中已经集成了强加密算法。然而，攻击者已经通过“侧信道”将目标从加密算法本身转移到这些算法的硬件/软件实现上。芯片测量。从硬件的角度来看，这种侧信道攻击可以在电路级和体系结构级实现。尽管在减轻侧信道攻击方面已经进行了大量研究，但这些解决方案缺乏灵活性、非系统性，并且开销很大。本研究的目标是开发一种通用的解决方案，协同结合架构级和电路级对策，以减轻所有主要类别的侧信道攻击，从而产生一种极其安全、高度灵活、低开销的数字系统设计方法。在这个概念验证项目中，将在两个级别进行初步研究。在体系结构级别，将开发新的体系结构支持，以减轻体系结构级别的定时和访问驱动的攻击。在电路层面，延迟不敏感三元逻辑将用于设计新的架构支持以及MIPS32 4k兼容嵌入式微处理器的其他关键组件。在架构级和电路级将评估抗侧信道攻击的有效性和效率。开发电路级和体系结构级攻击缓解教育模块。研究生和本科生，特别是来自代表性不足群体的学生，将参与这个项目。研究成果将通过期刊文章、会议报告和适当的网站传播给学术界和工业界。

Abstract: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer ProtectionEmbedded digital systems are ubiquitous and may contain sensitive information that could be used for malicious purposes if fallen into the wrong hands. Therefore, strong cryptographic algorithms have been incorporated inside these devices. However, attackers have switched their targets from the cryptographic algorithms themselves to the hardware/software implementations of these algorithms, through ?side-channel? chip measurements. From a hardware perspective, such side-channel attacks can be implemented at both the circuit-level and architecture-level. Although much research has been performed in mitigating side-channel attacks, these solutions are inflexible, unsystematic, and have high overhead. The goal of this research is to develop a universal solution that synergistically combines both architecture-level and circuit-level countermeasures for mitigating all major categories of side-channel attacks, to yield an extremely secure, highly flexible, low overhead digital system design methodology. In this proof-of-concept project, preliminary research will be carried out at both levels. At the architecture-level, novel architectural support to mitigate architecture-level timing and access-driven attacks will be developed. At the circuit-level, Delay-Insensitive Ternary Logic will be utilized to design the new architectural support as well as other key components of a MIPS32 4K-compatible embedded microprocessor. The effectiveness and efficiency of side-channel attack resistance at both architecture-level and circuit-level will be evaluated. Educational modules of circuit-level and architecture-level attack mitigation will be developed. Graduate and undergraduate students, especially from underrepresented groups, will be involved in this project. The research outcome will be disseminated to the academic and industrial communities through journal articles, conference presentations, and appropriate websites.