IRES Track I:Collaborative Research:Application-Specific Asynchronous Deep Learning IC Design for Ultra-Low Power

IRES 轨道 I：协作研究：超低功耗专用异步深度学习 IC 设计

• 批准号: 1951489
• 负责人: Jia Di
• 金额: $ 20万
• 依托单位: University of Arkansas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2020
• 资助国家: 美国
• 起止时间: 2020-09-01 至 2024-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1951489&HistoricalAwards=false
• 关键词: IRES; Track; Collaborative; Research; Application

This 3-year IRES Track I project recruits three cohorts of U.S. students to conduct research in China, with the major research goal as developing, fabricating, and testing an ultra-low power application-specific deep learning integrated circuit, and evaluating its performance through the integration with physical Internet-of-Things (IoT) edge computing devices. It brings together three research groups with unique expertise from University of Arkansas (ultra-low power asynchronous circuit design), University of South Alabama (context-aware memory design), and Peking University, China (deep learning algorithm development and optimization). The expected research outcomes will accelerate edge computing for a large variety of IoT applications such as advanced medical and elderly care systems and self-driving vehicles. Each year six U.S. student participants work onsite at Peking University for eight weeks, leveraging the onsite research facilities. The multicultural, multidisciplinary nature of this project provides a unique training and career preparation opportunity for the participating students, including multidisciplinary discussion, teamwork, effective communication, and technical writing. The PIs continue their prior efforts in recruiting student participants from underrepresented and minority groups, leveraging their contacts and the existing mechanisms at each university. The research outcomes and the student experience will be disseminated nation-wide for benefiting the research community and encouraging more students to participate in similar programs.Deep learning is transforming many modern Artificial Intelligence (AI) applications, in many of which deep learning has begun to exceed human performance. However, the superior performance of deep learning comes at the cost of extremely high computational complexity associated with large datasets. Therefore, deep learning algorithms are traditionally implemented in software and executed on powerful general-purpose cloud computing platforms. In contrast to the prevailing research in general-purpose counterparts, the application-specific deep learning IC has much lower power consumption, thereby ideal for integration with power-constrained IoT devices. This IRES project is to develop, fabricate, and test an ultra-low power deep learning integrated circuit (IC), and evaluate its performance through the integration with physical IoT edge computing devices. Technical innovations to be developed by the student participants include: 1) optimization of application-specific deep learning algorithms for alleviating the requirements of hardware implementation; 2) delay-insensitive asynchronous circuit design for substantially improved energy efficiency; and 3) context-aware memory development for power savings and low implementation cost. This project uniquely connects deep learning algorithm optimization, asynchronous circuit design, and memory optimization together to achieve a highly optimized system, which will benefit the semiconductor and AI societies at large by the revolutions in hardware-tailored deep learning algorithms and specialized computing hardware. It is expected that this research will demonstrate the advantages of application-specific deep learning hardware and layout the foundation of a new and promising direction for both academic research and industrial development.This project is jointly funded by the Office of International Science and Engineering (OISE) and the Established Program to Stimulate Competitive Research (EPSCoR).This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

这个为期3年的IRES Track I项目招募了三批美国学生来中国进行研究，主要研究目标是开发、制造和测试超低功耗专用深度学习集成电路，并通过与物理物联网（IoT）边缘计算设备的集成来评估其性能。它汇集了来自阿肯色大学（超低功耗异步电路设计）、南阿拉巴马大学（上下文感知存储器设计）和中国北京大学（深度学习算法开发和优化）的三个具有独特专业知识的研究小组。预期的研究成果将加速各种物联网应用的边缘计算，例如先进的医疗和老年护理系统以及自动驾驶车辆。每年，六名美国学生参与者在北京大学现场工作八周，利用现场研究设施。该项目的多元文化、多学科性质为参与的学生提供了独特的培训和职业准备机会，包括多学科讨论、团队合作、有效沟通和技术写作。 PI 继续之前的努力，利用他们的人脉和每所大学的现有机制，从代表性不足的群体和少数群体中招募学生参与者。研究成果和学生体验将在全国范围内传播，造福研究界，并鼓励更多学生参与类似项目。深度学习正在改变许多现代人工智能（AI）应用，其中许多应用深度学习已经开始超越人类的表现。然而，深度学习的卓越性能是以与大型数据集相关的极高计算复杂性为代价的。因此，深度学习算法传统上以软件形式实现，并在强大的通用云计算平台上执行。与通用型同类产品的流行研究相比，专用深度学习 IC 的功耗要低得多，因此非常适合与功率受限的物联网设备集成。该 IRES 项目旨在开发、制造和测试超低功耗深度学习集成电路 (IC)，并通过与物理物联网边缘计算设备的集成来评估其性能。学生参与者将开发的技术创新包括：1）优化特定应用的深度学习算法，以减轻硬件实现的要求； 2）延迟不敏感的异步电路设计，大幅提高能效； 3) 上下文感知存储器开发，以节省功耗并降低实施成本。该项目独特地将深度学习算法优化、异步电路设计和内存优化连接在一起，以实现高度优化的系统，这将通过硬件定制的深度学习算法和专用计算硬件的革命使整个半导体和人工智能社会受益。预计这项研究将展示专用深度学习硬件的优势，并为学术研究和产业发展奠定新的、有前途的方向的基础。该项目由国际科学与工程办公室（OISE）和刺激竞争性研究既定计划（EPSCoR）共同资助。该奖项反映了 NSF 的法定使命，并通过利用基金会的智力价值和更广泛的评估进行评估，认为值得支持。 影响审查标准。