SHF: Small: ADAPT: an Adaptive Delay-insensitive Asynchronous PlaTform for energy efficiency across wide dynamic ranges

近年来半导体技术的进步使得数十亿个晶体管可以集成在同一芯片上，这使得功耗成为最关键的设计限制。随着晶体管特征尺寸的不断缩小，主流时钟同步逻辑已经开始面临越来越多的挑战，本研究旨在开发一种创新的异步数字处理器设计方法和能效平台，提供平衡的功率和速度权衡，以在所有情况下为各种应用提供“恰到好处”的性能。在我们的新的设计方法中，给定应用场景和设计约束的信息，选择合适的异步处理单元，并确定并行体系结构中的核的数量。这一吞吐量分析步骤通过包括广泛的处理元素和采用细粒度表征过程来优化。在处理器运行期间，监控输入数据速率和系统利用率，并将其与用户偏好进行比较，以确定有多少核应该保持活动状态，并相应地调整电源电压。实现了基于历史的预测机制，以实现准确而高效的工作负载预测。动态电压调整的集中式和分布式电压架构将在广泛的动态范围内进行比较，并评估各种低压栅极设计在促进极端电压调整以降低功率方面的作用。在各种约束和用户设置下，将设计、布局和模拟一系列原型电路。将对结果进行总结和分析，以进行性能评估和设计方法的进一步优化。这项研究的结果可能会对电池供电的移动计算和通信设备行业产生影响，因为这些产品可以提供更长的电池寿命、更高的可靠性和更低的成本。

Advances in semiconductor technology in recent years allow billions of transistors to be integrated on the same chip, which makes power consumption the most critical design constraint. While the prevailing clocked synchronous logic has started to face more and more challenges as the transistor feature size continues to shrink, this research is to develop an innovative asynchronous digital processor design methodology and platform for energy efficiency, which provide a balanced power-speed tradeoff to deliver "just right" performance under all circumstances across a large variety of applications. In our novel design methodology, given information for an application scenario and design constraints, appropriate asynchronous processing elements are selected and the number of cores in a parallel architecture is determined. This throughput analysis step is optimized by including a wide range of processing elements and by employing a fine-grained characterization process. During processor operation, the input data rate and the system utilization are monitored and compared with user preference to determine how many cores should remain active and also to adjust the supply voltage accordingly. A history-based forecasting mechanism is implemented for accurate yet efficient workload prediction. Centralized and distributed voltage architectures for dynamic voltage scaling will be compared across wide dynamic ranges, along with the evaluation of various low voltage gate designs in facilitating extreme voltage scaling for power reduction. A series of prototype circuits will be designed, laid out, and simulated under various constraints and user settings. The results will be summarized and analyzed for performance evaluation and further optimization in the design methodology. Outcomes of this research have the potential to impact the battery-powered mobile computing and communication device industry, by enabling products that offer longer battery life, enhanced reliability, and reduced cost.