SHF: Small: ADAPT: an Adaptive Delay-insensitive Asynchronous PlaTform for energy efficiency across wide dynamic ranges

近年来，半导体技术的进步使得数十亿个晶体管可以集成在同一芯片上，这使得功耗成为最关键的设计约束。随着晶体管特征尺寸的不断缩小，当前流行的时钟同步逻辑开始面临越来越多的挑战，本研究旨在开发一种创新的异步数字处理器设计方法和平台，以提高能效，提供平衡的功率-速度权衡，在各种应用的所有情况下提供“恰到好处”的性能。在我们的新的设计方法，给定的应用场景和设计约束的信息，选择适当的异步处理元件，并确定在一个并行架构的核心的数量。通过包括广泛的处理元件和采用细粒度表征过程来优化该吞吐量分析步骤。在处理器操作期间，输入数据速率和系统利用率被监控，并与用户偏好进行比较，以确定应保持活动的内核数量，并相应地调整电源电压。实现了基于历史的预测机制，以实现准确而有效的工作负载预测。动态电压调整的集中式和分布式电压架构将在宽动态范围内进行比较，沿着评估各种低电压栅极设计，以促进极端电压调整，降低功耗。一系列原型电路将在各种约束和用户设置下进行设计、布局和仿真。最后将对结果进行总结与分析，以作为评估效能与进一步优化设计方法的依据。这项研究的成果有可能影响电池供电的移动的计算和通信设备行业，使产品提供更长的电池寿命，增强的可靠性，降低成本。

Advances in semiconductor technology in recent years allow billions of transistors to be integrated on the same chip, which makes power consumption the most critical design constraint. While the prevailing clocked synchronous logic has started to face more and more challenges as the transistor feature size continues to shrink, this research is to develop an innovative asynchronous digital processor design methodology and platform for energy efficiency, which provide a balanced power-speed tradeoff to deliver "just right" performance under all circumstances across a large variety of applications. In our novel design methodology, given information for an application scenario and design constraints, appropriate asynchronous processing elements are selected and the number of cores in a parallel architecture is determined. This throughput analysis step is optimized by including a wide range of processing elements and by employing a fine-grained characterization process. During processor operation, the input data rate and the system utilization are monitored and compared with user preference to determine how many cores should remain active and also to adjust the supply voltage accordingly. A history-based forecasting mechanism is implemented for accurate yet efficient workload prediction. Centralized and distributed voltage architectures for dynamic voltage scaling will be compared across wide dynamic ranges, along with the evaluation of various low voltage gate designs in facilitating extreme voltage scaling for power reduction. A series of prototype circuits will be designed, laid out, and simulated under various constraints and user settings. The results will be summarized and analyzed for performance evaluation and further optimization in the design methodology. Outcomes of this research have the potential to impact the battery-powered mobile computing and communication device industry, by enabling products that offer longer battery life, enhanced reliability, and reduced cost.