Scalable Array Packaging for Optoelectronic Components

光电器件阵列封装ERC创新计划A。2 PI，Nasser Peyghambarian，亚利桑那大学Connie Chang-Hasnain和Ming Wu，EECS，加州大学伯克利分校作为集成接入网络工程研究中心（CIAN）的一部分，该项目将研究用于光电元件的可扩展和新型封装，例如垂直腔面发射激光器（VCSEL）和可调谐滤波器阵列。这将满足一个主要需求，使研究小组专注于新的设备，提出适合系统和测试平台的先进特性的组件。这笔资金将用于支持一名具有光电子和光学微机电系统（MEMS）工业实践和创新专业知识和经验的研究工程师。这个职位的特别候选人是S博士。Patra，拥有16年的工艺开发和转移行业经验。他将带来关键的技能基础，以提高推力III的能力，提供先进的概念验证设备的测试台，并将研究思路转化为系统架构。在光电子元件行业，封装成本占目前组件组装制造费用的60 - 80%，而在电子元件中仅占10%。为了在CIAN中的接入网络中部署这里提出的新颖的光子和光电组件，必须解决封装成本。计划的策略是，首先，将封装视为设备设计的一部分，而不是事后的想法;其次，尽可能追求芯片级封装。芯片级封装目前广泛应用于IC和MEMS工业，以减少占地面积和封装成本。该项目包括两个主要组成部分的晶圆级，低成本，密封封装。第一个包括高速VCSEL阵列的工艺和封装，第二个包括面内波导阵列。第一个项目的挑战是需要垂直对齐的多个芯片，而第二个项目的挑战是需要对齐芯片的两个面。这涵盖了光纤耦合问题中最具挑战性的部分：面发射二维阵列和边发射器件两个面的耦合。随着这两种拓扑结构的解决方案，开发的结果将很容易扩展到所有的光电器件。Patra博士在这两种封装方面都有丰富的工业经验，特别是在光电封装的热、机械和电气设计方面。他的领导将有助于准备研究生，包括包装考虑到设备和材料设计，并在交叉点工作。该提案的主要科学目标和智力价值是开发一种可扩展的工艺，并提出一个通用平台来组装各种光电器件，这些光电器件需要在表面法线和面内方向上进行光耦合，一系列电信号频率和操作条件。更广泛的影响将是通过提供通用封装平台来有效弥合光电器件和系统之间的差距。拟议的工作将有助于研究人员更容易地在中心内部和与行业合作。新的工艺将是基本的，可以很容易地扩展到所有的边缘发射和表面发射的光电器件。这项工作将是重要的低成本，高吞吐量的光电子器件阵列的制造。CIAN光子学试验台的目的是成为第一个针对通信系统的跨学科研究的研究设施，从基础设备到子系统再到系统。有了Patra博士带来的包装技术，Thrust 3研究人员发明的设备将能够更积极地参与测试。由于CIAN赞助REU学生和高中外展计划，这项拟议的工作将为本科生和高中生提供更好的准备与真实的世界的做法和研究经验。

Array Packaging for Optoelectronic ComponentsERC Innovation Program A. 2PI, Nasser Peyghambarian, University of ArizonaConnie Chang-Hasnain and Ming Wu, EECS, University of California, BerkeleyAs part of the Engineering Research Center for Integrated Access Networks (CIAN), this project will investigate scalable and novel packaging for optoelectronic components, e.g. vertical cavity surface emitting laser (VCSEL) and tunable filter arrays. This will fill a major need to enable research groups focusing on novel devices to bring forth components suitable for advanced characterization in systems and testbeds. The funding will support a research engineer with expertise and experience of industrial practice and innovation in optoelectronics and optical micro-electro-mechanical systems (MEMS). The particular candidate identified for this position is Dr. S. Patra, with 16 years of industry experience in process development and transfer. He will bring critical skill base to enhance Thrust III's capability to deliver advance proof-of-concept devices to test beds, and translate research ideas into system architecture.In the optoelectronic components industry, the package cost accounts for 60 to 80% of current manufacturing expenses in component assembly, while it is only 10% in electronic components. To deploy the novel photonic and optoelectronic components proposed here in access networks in CIAN, one must address the packaging cost. The planned strategy is, first, to treat packaging as part of the device design rather than an afterthought; and, second, to pursue chip-scale packaging whenever possible. Chip-scale packaging is now widely employed in IC and MEMS industries to reduce footprint and packaging cost. The project includes two major components of wafer-level, low-cost, hermetic packaging. The first one includes the process and package of a high-speed VCSEL array and the second with in-plane waveguide arrays. The challenge for the first project is the need of multiple chips requiring vertical alignments, while for the second is on requiring alignment of both facets of a chip. This covers the most challenging parts of fiber coupling problems: surface-emitting 2D array and coupling of both facets of edge-emitting devices. With solutions to both topologies, the developed results will be readily extended to all optoelectronic devices. Dr. Patra has significant industrial experiences on both types of packaging, particularly on thermal, mechanical and electric designs of optoelectronic packages. His leadership will help to prepare the graduate students to include packaging considerations into device and material designs and to work at the intersection. The key scientific goals and intellectual merit of this proposal is to develop a scalable process and bring forth a common platform to assemble diverse optoelectronic devices, requiring optical coupling in both surface-normal and in-plane directions, a range of electrical signal frequencies and operating conditions.The broader impacts will be in effectively bridging the gap between optoelectronic devices and systems by providing a universal packaging platform. The proposed work will facilitate researchers to collaborate more readily within the Center and with industry. The new processes will be fundamental and can be readily extended to all edge-emitting and surface-emitting optoelectronic devices. This work will be important for low-cost, high through-put manufacturing of arrays of optoelectronic devices. The purpose of the CIAN Photonics Testbed is to be the first research facility to target cross-disciplinary research on communications systems spanning from fundamental devices to subsystems to systems. With the packaging know-how brought forth by Dr. Patra, the devices invented by Thrust 3 researchers will be able to participate more actively in the testbed. As CIAN sponsors REU students and high school outreach programs, this proposed work will provide better preparation for undergraduate and high school students with real world practices and research experiences.