SHF: Small: Formal Synthesis of Low-Energy Signal Processing Systems Relying on Controlled Timing-Error Acceptance

提高嵌入式和移动系统的能源效率是一个主要的设计挑战。这种系统涉及复杂的视听处理、识别和通信算法，大量利用数字信号处理（DSP）架构。本文提出了一种系统的策略来降低DSP子系统的能耗，从而朝着新一代低能耗嵌入式应用迈出了重要的一步。该提案背后的主要前提是，信号处理算法可以以一种精细控制的方式接受一定数量的时序误差，以换取显著的节能。信号处理算法有一个内在质量底限，由量化和舍入噪声设定。传统的最坏情况边际设计范例是非常不理想的，通过接受少量低概率的时间误差，可以节省超过50%的能源。该提案下的研究将导致正式分析和综合框架的发展，用于集成到硬件综合流程中，支持超低能量容错DSP系统的系统设计。时序误差受控接受流程必须从根本上基于质量-能量（Q-E）权衡的新正式概念，这是允许误差的信号处理所独有的，并且允许在同一框架内一致地处理其他Q-E技术，例如近似信号处理。为此，该项目的目标有两个方面：(i)在给定的输入统计数据和质量-能量预算下，正式开发控制时间误差接受的模型和分析技术；（ii）开发一个全面的综合流程，允许将多种Q-E技术应用于质量、能源、面积和性能目标的共同优化，用于一般可以容忍少量错误的大类算法。这项工作的结果将能够自动探索联合算法和架构权衡，以实现一般质量和能量调谐的错误允许系统。新的控制时序误差范例将促进集成电路和数字系统能源效率的持续改进，其中超低能耗操作将使使用迄今为止不可实现的便携式，植入式，无线和自主系统成为可能。

Improving energy efficiency of embedded and mobile systems is a major design challenge. Such systems involve complex algorithms for audiovisual processing, recognition, and communication that heavily utilize digital signal processing (DSP) architectures. This proposal advances a systematic strategy to reduce energy consumption of DSP sub-systems and thereby make major strides towards a new generation of low-energy embedded applications. The main premise behind the proposal is that signal processing algorithms may accept, in a finely controlled manner, some amount of timing errors in return for significant energy savings. Signal processing algorithms have an intrinsic quality floor, set by quantization and roundoff noise. A traditional design paradigm of worst-case margining is highly suboptimal, and by accepting a small amount of low-probability timing errors, significant energy savings of more than 50% are possible.Research under this proposal will result in the development of a formal analysis and synthesis framework for integration into a hardware synthesis flow that supports systematic design of ultra low-energy error-permissive DSP systems. A flow for controlled acceptance of timing errors must fundamentally be based on a new formal notion of quality-energy (Q-E) tradeoff, which is unique to error-permissive signal processing, and which will allow treatment of other Q-E techniques, such as approximate signal processing, consistently within the same framework. To this end, the goals of this project are two-fold: (i) to formally develop models and analysis techniques for controlled timing-error acceptance under given input statistics and quality-energy budgets, and (ii) to develop a comprehensive synthesis flow that allows multiple Q-E techniques to be applied to the co-optimization of quality, energy, area and performance objectives for a large class of algorithms that can generally tolerate a small amount of errors. Results of this work will enable automatic exploration of joint algorithm and architecture tradeoffs for implementation of general quality- and energy-tuned error-permissive systems. The new controlled timing error paradigm will facilitate sustained improvement in the energy efficiency of integrated circuits and digital systems, where ultra low-energy operation will enable use of hitherto infeasible portable, implantable, wireless and autonomous systems.