CSR: Small: Scalable Effort Design: Exploiting Algorithmic Resilience for Energy Efficiency

用于将算法转换为硬件实现的设计过程遵循规范和实现需要在布尔或数值意义上等效的公理。然而，来自几个有趣的应用领域的算法表现出？固有的弹性呢?，从而通过放宽对完全等效实现的要求，为性能和功率优化提供了全新的途径。我们探索可扩展的努力硬件设计作为一种方法来挖掘固有弹性的水库，并将其转化为高效的硬件实现。我们确定了设计抽象（电路、微架构和算法）的每个级别的机制，这些机制可用于改变生成正确（精确）结果所花费的计算工作量，并将它们暴露为实现中的控制旋钮，以实现更高的能源效率。要充分发挥算法弹性的潜力，就需要在不同设计抽象层次上对缩放机制进行协同跨层优化。我们研究了通过缩放机制的跨层优化可能实现的权衡的性质，并开发了确定最佳工作点（就不同的缩放机制而言）的技术，以最大化任何给定输出质量水平的性能或能源效率。拟议的研究将开发新的设计方法，使识别和挖掘等新兴应用的硬件实现达到前所未有的性能和能源效率水平。我们将通过出版物、开源设计的发布、集成到VLSI设计和片上系统课程材料以及通过普渡大学(Purdue？nanoHub。

The design processes used to convert algorithms to hardware implementations have obeyed the axiom that the specification and implementation need to be equivalent in a Boolean or numerical sense. However, algorithms from several interesting application domains exhibit the property of ?inherent resilience?, thereby offering entirely new avenues for performance and power optimization by relaxing the requirement of an exact equivalent implementation.We explore scalable effort hardware design as an approach to tap the reservoir of inherent resilience and translate it into highly efficient hardware implementations. We identify mechanisms at each level of design abstraction (circuit, micro-architecture and algorithm) that can be used to vary the computational effort expended towards generation of the correct (exact) result, and expose them as control knobs in the implementation to achieve improved energy efficiency. Fully exploiting the potential of algorithmic resilience requires synergistic cross-layer optimization of scaling mechanisms at different levels of design abstraction. We investigate the nature of the tradeoffs that are possible through cross-layer optimization of scaling mechanisms, and develop techniques to determine the optimal operating point (in terms of the different scaling mechanisms) that maximizes performance or energy efficiency for any given level of output quality.The proposed research will develop new design approaches that can enable unprecedented levels of performance and energy efficiency in hardware implementations of emerging applications such as recognition and mining. We will disseminate our results through publications, release of open source designs, integration into VLSI Design and System-on-Chip course material, and through Purdue?s nanoHub.