EAGER: The Exploration of Memory Hierarchy Design and Optimization for Multi-core Systems

最近，处理器和内存速度之间的差距越来越大；这种差距被称为内存墙？有问题。内存性能对整体系统性能有着决定性的影响，尤其是对于以数据为主的应用程序。此外，内存通常占据多核系统集成芯片的一半表面；所需的内存总量也是多核CPU制造成本和芯片尺寸的主要贡献者。内存也决定了功耗，因为内存和公交车会消耗大量能源。记忆墙？当处理器部分的吞吐量由多核体系结构推动时，问题变得更加严重。在这个方案中，PI正在进行研究，以解决？并为多核系统中的存储器层次结构设计和配置开发潜在的变革性方法。不同的存储体系结构可以产生不同的解决方案，具有不同的成本和不同的性能。内存大小、内存配置和内存架构将针对多核架构同时进行优化，以有效和高效地实现更高的性能。

Recently, there has been a growing disparity between processor and memory speeds; this disparity is called the ?memory wall? problem. Memory performance has a dominating effect on overall system performance, especially for the data-dominated applications. Also, memory usually occupies half of the surface of the integrated chip of the multi-core system; the total amount of memory required is also a main contributor of the manufacturing cost and the chip size of the multi-core CPU. Memory also dictates the power consumption, since memories and buses consume large quantities of energy. The ?memory wall? problem becomes even more serious when throughput in the processor part is propelled by multi-core architectures.In this proposal, the PI is carrying out research to address the ?memory wall? problem and to develop potentially transformative approaches for memory hierarchy design and configuration in multi-core systems. Different memory architectures can lead to different solutions with different costs and with different performances. Memory size, memory configuration, and memory architecture will be optimized simultaneously for multi-core architectures in order to effectively and efficiently achieve higher performance.