SHF: Small: Integrating Compiler and Architecture Design to Boost Timing Speculation

这个项目研究了共同设计编译器和硬件的艺术和科学，用于电路级时序推测，从而实现可靠的，高性能的计算机系统。时序推测，一个令人兴奋的，前瞻性的硬件设计替代方案，允许设计人员放弃悲观的设计准则，从而从硅提取更多的性能。不幸的是，当代编译器技术对时序推测的支持不足。这项研究开发了新的设计范例，允许编译器和架构进行联合优化，以构建高效的时序推测系统，这是一个显着的工业和社会效益。推广工作激励学生追求计算机科学和工程的研究生学习。考虑到时间推测的前景，但现有工作的重点普遍向下，有针对性的代码生成解决了系统堆栈中被忽视的部分，并提供了诱人的可能性。 本研究发展了时序感知编译，应用指令级错误率模型来分析和优化指令序列。通过生成专门针对定时推测的二进制文件，编译器的目标是显着减少需要动态校正的定时错误的发生率。这通过降低回收成本来扩大时机投机的范围。这使系统能够以更高的时钟频率工作，或者通过更低的电源电压实现更高的能效。该研究通过机器学习技术开发了紧凑的定时错误率模型，并确定了如何使用现代编译器中现有的流分析来驱动这些错误率模型。编译器扩展了现有的代码优化，以包括在分析阶段生成的计时错误的估计影响。编译器技术正在被用来研究集成时序推测系统的新设计范式，包括协同设计和协同优化的架构和编译器。

This project examines the art and science of co-designing compilers and hardware for circuit-level timing speculation thereby enabling reliable, high-performance computer systems. Timing speculation, an exciting, forward-looking hardware design alternative, allows designers to abandon pessimistic design guidelines and consequently extract more performance from the silicon. Unfortunately, timing speculation has been under-served by contemporary compiler technologies. This research develops novel design paradigms that allow the compiler and architecture to be jointly optimized to build highly effective timing speculative systems, a significant industrial and societal benefit. Outreach efforts motivate students to pursue graduate study in computer science and engineering. Given the promise of timing speculation but the prevailing downward focus of existing work, targeted code generation addresses neglected portions of the system stack and offers enticing possibilities. This research develops timing-aware compilation that applies instruction-level error rate models to analyze and optimize instruction sequences. By generating binaries specifically targeted for timing speculation, the compiler aims to significantly reduce incidence of timing errors which demand dynamic correction. This extends the reach of timing speculation by reducing recovery cost. This allows systems to operate at higher clock frequencies or enables better energy-efficiency through lower supply voltages. The research develops compact timing error rate models through machine learning techniques and determines how existing flow analysis present in modern compilers could be used to drive these error rate models. The compiler extends existing code optimizations to include the estimated impact of timing errors generated during analysis phases. The compiler technology is being used to examine new design paradigms for integrated timing speculative systems which include co-designed and co-optimized architectures and compilers.