SHF: Small: Lifetime Aware System Architecture Design of Single-Chip Embedded Multiprocessors

通过减小晶体管和互连尺寸，硅集成电路的制造工艺的改进也导致了如果没有正确设计和使用则会磨损的集成电路。也就是说，由于诸如增加的操作功率和温度以及随着尺寸减小而不理想的缩放效果等因素，它们将无法长期持续工作。如果不给予补偿，故障的数量预计将呈指数级增长。因此，日益增加的磨损故障率将需要为所有系统设计寿命可靠性方法，而不仅仅是那些安全关键任务。一种新的可靠性设计方法，以帮助设计成本效益的寿命增强系统正在开发的嵌入式计算应用。正在设计的系统是与芯片上的网络互连的多处理器。网络中的网络交换机用于在处理器之间路由信息。设计方法包括选择开关的数量及其互连，选择要连接到开关的处理器和存储器的类型，选择软件程序将在哪些处理器上运行，以及选择每个处理器将工作的电压和时钟速率。这些设计决策中的每一个都可能对集成电路的寿命产生重大影响。设计方法学需要搜索通过一个巨大的设计方案，每个需要一个计算昂贵的计算的平均时间到故障的系统设计。基于蚁群的优化技术被用来探索这个大的设计空间和硬件加速技术，如图形处理单元和现场可编程门阵列，被用来加快平均故障时间的计算。嵌入式单芯片多处理系统的应用将继续在从个人计算设备到生物监测系统到消费电子产品的广泛应用中增长。嵌入式计算应用的持续增长是经济的主要驱动力，因为它提高了个人生产力。这项研究能够在制造过程中进行更深层次的扩展，从而实现更强大的系统，因为这些新的集成电路将继续可实现，即使其中的单个组件预计会在制造时过早失效或可能无法完全工作。研究成果将通过研究生课程和研究文章传播，有些主题将被引入初级/高级课程。

The improvements in manufacturing processes for silicon integrated circuits, through the reduction in transistor and interconnect sizes, also give rise to integrated circuits that will wear out if not designed and used properly. That is, they will fail to continue to work over a long period due to factors such as increased operating power and temperature, and un-ideal scaling effects as the sizes are reduced. The number of failures, when left uncompensated, is expected to grow exponentially. Thus, the increasing wear-out failure rates will require design-for-lifetime reliability methodologies for all systems, not just those with safety critical missions. A novel design-for-reliability methodology to aid in the design of cost-effective lifetime-enhanced systems is being developed for embedded computing applications. The systems being designed are multiprocessors that are interconnected with a network on the chip. Network switches in the network are used to route information among the processors. The design methodology includes choosing the number of switches and their interconnection, choosing the types of processors and memories to be connected to the switches, selecting which processors the software programs will run on, and selecting the voltage and clock rate that each of the processors will operate at. Each of these design decisions can have a major impact on the lifetime of an integrated circuit. The design methodology requires searching through an enormously large set of design alternatives, each requiring a computationally expensive calculation of the mean-time-to-failure for the system being designed. An ant colony based optimization technique is used to explore this large design space and hardware acceleration techniques, such as graphics processing units and field programmable gate arrays, are used to speed the mean-time-to-failure calculations. The application of embedded single-chip multiprocessing systems will continue to grow across a broad spectrum of applications from personal computing devices, to biological monitoring systems, to consumer electronics. This continued growth in embedded computing applications is a major driver in the economy as it improves personal productivity. This research enables deeper scaling in the manufacturing process, and thus more capable systems, since these new integrated circuits will continue to be implementable even when individual components within them are expected to fail early or possibly are not fully working when manufactured. The research results will be disseminated through graduate courses and research articles, with some topics being introduced into a Junior/Senior level course.