SBIR Phase I: Creating Delay-tolerant, Asynchronous Network Interfaces

这个小型企业创新研究（SBIR）第一阶段项目解决了集成电路（IC）片上系统（SoC）产品中日益严重的问题。每个这样的产品可能有数十亿个晶体管和小于可见光波长的特征尺寸。现代半导体工艺给IC制造带来了新的挑战，因为晶体管可变性显著增加，并且需要大大降低功耗。Blendics开发了一种包装技术，使每个SoC子系统看起来好像是异步的，并且独立于其邻居，从而减少了参数变化的不良影响，并实现了动态功耗降低技术。然而，这些包装器使用手工设计方法是不够的。这项研究的目标是自动化这一设计任务，使这些包装的广泛使用在经济上具有吸引力，仍然能够克服不可避免的过程可变性的挑战。建议的研究混合异步和同步设计技术，以保留传统工具的优点，同时避免其缺点。结果将是一个设计自动化工具，生成一个子系统？的包装器从其电路规格。如果该工具能够以最少的额外设计工作量为各种子系统生成包装器，则将取得成功。该项目更广泛的影响/商业潜力来自于SoC技术在电话、娱乐产品、医疗保健设备、汽车设备、计算机和现代生活中大量存在的许多其他应用中的应用。单个SoC的生产成本可能非常便宜，但设计和制造先进的定制SoC的第一个副本的成本目前约为8500万美元。随着新的半导体工艺的引入，这种成本必然会上升。这种设计成本的大部分与克服与子系统之间的全局连接相关的时序约束有关。这就是所提出的包装器技术所解决的问题。因此，为创建片上网络开发一个全球标准是价值17亿美元的硅知识产权业务领域的一个重大机遇。这样的标准可以克服半导体行业在向前发展时面临的严重技术问题。如果没有一个好的解决方案来解决工艺可变性的问题，SoC的第一个副本的成本可能会变得如此之高，以至于只有最大批量的产品才有良好的商业意义。因此，公众可能无法访问医疗和安全应用中的重要SoC产品。

This Small Business Innovation Research (SBIR) Phase I project addresses a growing problem in integrated circuit (IC) system-on-chip (SoC) products. Each such product may have billions of transistors and a feature size of less than the wavelength of visible light. Modern semiconductor processes bring new challenges to IC fabrication because of significantly increased transistor variability and the need to greatly reduce power dissipation. Blendics has developed a wrapper technology that makes each SoC subsystem appear as if it were asynchronous and independent of its neighbors, thereby reducing the undesirable effects of parameter variability and enabling dynamic power reduction techniques. However, the use of manual design methods for these wrappers is inadequate. The goal of this research is to automate this design task making the widespread use of these wrappers economically attractive and still capable of overcoming the inevitable process variability challenges. The proposed research blends asynchronous and synchronous design techniques in order to retain the advantages of conventional tools while avoiding their disadvantages. Results will be a design-automation tool that generates a subsystem?s wrapper from its circuit specification. Success will be achieved if this tool generates wrappers for a broad variety of subsystems with a minimum of additional designer effort.The broader impact/commercial potential of this project arises from the fact that SoC technology finds use in phones, entertainment products, health-care devices, automotive equipment, computers and many other applications that abound in modern life. An individual SoC may be seductively inexpensive in production, but the cost to design and fabricate the first copy of an advanced, custom SoC is today approximately $85 million US dollars. This cost is bound to rise as new semiconductor processes are introduced. Much of this design cost is associated with overcoming the timing constraints associated with global connectivity among the subsystems. This is the problem that the proposed wrapper technology addresses. Thus, developing a world-wide standard for creating a network-on-chip is a significant opportunity in the $1.7B silicon intellectual-property business sector. Such a standard could overcome the serious technical problem the semiconductor industry faces as it moves forward. In the absence of a good solution to this problem of process variability, the cost of the first copy of an SoC is likely to become so high that only the highest volume products will make good business sense. As a result, public access may be denied important SoC products in medical and safety applications.