STTR PHASE I: Blended Clocked and Clockless Integrated Circuit Systems

STTR 第一阶段：混合时钟和无时钟集成电路系统

• 批准号: 0741055
• 负责人: Jerome Cox
• 金额: $ 14.99万
• 依托单位: Blendics, Inc.
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-01-01 至 2008-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0741055&HistoricalAwards=false
• 关键词: STTR; PHASE; Blended; Clocked; Clockless

This Small Business Technology Transfer Phase I research project will demonstrate a globally asynchronous, locally synchronous (GALS) methodology for the design of large-scale, deep-submicron, System-on-Chip (SoC) integrated circuits fabricated in Field-Programmable Gate Arrays (FPGAs). The methodology utilizes a Delay-Insensitive (DI) interconnect between conventionally clocked subsystems. The interconnect components are bundled data paths and a set of control elements whose designs are DI and hazard-free across processes and submicron scaling. These control elements are defined by Petri net models or their trace theory equivalents. Prototype software has been developed to synthesize, from their defining models, the required logic for these elements. Hazards are identified, logic hazards eliminated and metastability hazards managed. The methodology, in contrast to other approaches, allows the synthesis of a variety of arbiters from their models and includes novel stability detectors that can be implemented in FPGAs. The proposed work will improve the reliability, breadth and ease-of-use of the synthesis software and demonstrate a significant multiprocessor FPGA architecture. The proposed integrated circuit design methodology can substantially decrease the difficulty of designing billion-transistor, integrated-circuits for the SoCs of the future. The proposed GALS methodology will be introduced in the increasingly popular FPGA sector where other clockless designs have failed to leave the research laboratories. The proposed methodology has the potential to markedly decrease design cost and time-to-market of the large, specialized systems of the future.

这个小型企业技术转移第一阶段研究项目将展示一种全局异步、本地同步 (GALS) 方法，用于设计在现场可编程门阵列 (FPGA) 中制造的大规模、深亚微米片上系统 (SoC) 集成电路。该方法利用传统时钟子系统之间的延迟不敏感 (DI) 互连。互连组件是捆绑的数据路径和一组控制元件，其设计是跨工艺和亚微米缩放的 DI 和无危险的。这些控制元素由 Petri 网模型或其等价迹理论定义。原型软件的开发是为了根据其定义模型综合这些元素所需的逻辑。识别危险、消除逻辑危险并管理亚稳态危险。与其他方法相比，该方法允许从模型中合成各​​种仲裁器，并包括可在 FPGA 中实现的新型稳定性检测器。所提出的工作将提高综合软件的可靠性、广度和易用性，并展示重要的多处理器 FPGA 架构。所提出的集成电路设计方法可以大大降低为未来 SoC 设计十亿晶体管集成电路的难度。所提出的 GALS 方法将被引入日益流行的 FPGA 领域，而其他无时钟设计未能离开研究实验室。所提出的方法有可能显着降低未来大型专业系统的设计成本和上市时间。