STTR PHASE I: Blended Clocked and Clockless Integrated Circuit Systems

这个小企业技术转移第一阶段研究项目将展示一个全球异步，本地同步（GALS）的方法，用于设计大规模，深亚微米，系统级芯片（SoC）集成电路制造的现场可编程门阵列（FPGA）。该方法利用传统时钟子系统之间的延迟不敏感（DI）互连。互连组件是捆绑的数据路径和一组控制元件，其设计是跨工艺和亚微米尺度的DI和无危害的。这些控制元素由Petri网模型或其迹理论等价物定义。已经开发了原型软件，以便从其定义模型中综合这些要素所需的逻辑。识别危险，消除逻辑危险，管理亚稳态危险。与其他方法相比，该方法允许从其模型合成各种仲裁器，并包括可以在FPGA中实现的新型稳定性检测器。所提出的工作将提高合成软件的可靠性，广度和易用性，并展示一个重要的多处理器FPGA架构。所提出的集成电路设计方法可以大大降低设计未来SoC的十亿晶体管集成电路的难度。拟议的GALS方法将被引入日益流行的FPGA领域，其他无时钟设计未能离开研究实验室。所提出的方法有可能显着降低设计成本和上市时间的大型，专业化的系统的未来。

This Small Business Technology Transfer Phase I research project will demonstrate a globally asynchronous, locally synchronous (GALS) methodology for the design of large-scale, deep-submicron, System-on-Chip (SoC) integrated circuits fabricated in Field-Programmable Gate Arrays (FPGAs). The methodology utilizes a Delay-Insensitive (DI) interconnect between conventionally clocked subsystems. The interconnect components are bundled data paths and a set of control elements whose designs are DI and hazard-free across processes and submicron scaling. These control elements are defined by Petri net models or their trace theory equivalents. Prototype software has been developed to synthesize, from their defining models, the required logic for these elements. Hazards are identified, logic hazards eliminated and metastability hazards managed. The methodology, in contrast to other approaches, allows the synthesis of a variety of arbiters from their models and includes novel stability detectors that can be implemented in FPGAs. The proposed work will improve the reliability, breadth and ease-of-use of the synthesis software and demonstrate a significant multiprocessor FPGA architecture. The proposed integrated circuit design methodology can substantially decrease the difficulty of designing billion-transistor, integrated-circuits for the SoCs of the future. The proposed GALS methodology will be introduced in the increasingly popular FPGA sector where other clockless designs have failed to leave the research laboratories. The proposed methodology has the potential to markedly decrease design cost and time-to-market of the large, specialized systems of the future.