Advanced Modeling and Design of High-Performance ADC-Based Serial Links

智能优点：这项工作中提出的高速串行链路体系结构和设计技术旨在显著提高芯片间互连的能效和带宽密度，这是未来计算系统继续扩展所必需的。虽然通过使用模拟/混合信号均衡器在提高串行链路数据速率方面取得了重大进展，但模拟/混合信号均衡器可以补偿的通道损失量是有限的，在将这些电路扩展到纳米技术方面也存在挑战。这促使在芯片间互连接收器设计中使用基于模数转换器的模拟前端。这项工作的研究目标是开发适用于未来计算系统的高性能、高能效的基于转换器的高速串行链路体系结构。为了实现这一目标，将开发基于转换器的串行链路的超高速统计建模优化框架，该框架研究分辨率和模拟/数字均衡复杂性之间的权衡，并在建议的架构的设计中加以利用。将开发新的电路拓扑，以实现高效的调制、灵活的发射机以及在转换器中嵌入部分模拟均衡。系统级优化与电路级精度和新的超高效电路拓扑相结合，使架构能够利用更多的数字均衡，其效率随着每一代技术的发展而提高。广泛影响：这种基于转换器的串行链路架构提供的互连带宽容量爆炸式增长，将允许实现许多变革性应用，例如能够实现触发器/S性能的未来智能移动设备、多通道高分辨率磁共振成像，以及气候建模和蛋白质折叠模拟所需的亿级超级计算机。用提出的优化框架开发的互连架构不仅将对半导体行业产生广泛影响，还将对整个国家的可持续性和安全产生广泛影响，因为它将大幅降低这些集成系统的能源需求。该项目将包括一个涉及2名博士和3名本科生的跨学科教育方案，并承诺开展几项有吸引力的外联活动，以促进妇女和少数群体的代表性。项目成果将通过列入题为“高速链路电路和系统”的研究生课程的教学大纲和网站，以及通过在国内和国际期刊和会议上发表来广泛传播。

Intellectual Merit: The high-speed serial link architectures and design techniques proposed in this work aim to significantly improve inter-chip interconnect energy efficiency and bandwidth density, which is necessary for continued scaling of future compute systems. While significant progress has been made in increasing serial link data rates through the use of analog/mixed-signal equalization, there are limits to the amount of channel loss that analog/mixed-signal equalizers can compensate and also challenges in scaling these circuits to nanometer technologies. This motivates the use of analog-to-digital converter-based analog front ends in inter-chip interconnect receiver design. The work's research goal is to develop high-performance energy-efficient converter-based high-speed serial link architectures applicable to future computing systems. To accomplish this goal, an ultra-fast statistical-modeling optimization framework for converter-based serial links that investigates trade-offs in resolution and analog/digital equalization complexity will be developed and leveraged in the design of the proposed architecture. Novel circuit topologies will be developed that enable efficient modulation agile transmitters and the embedding of partial analog equalization in the converter. The combination of system level optimization with circuit-level accuracy and new ultra-efficient circuit topologies enables architectures capable of leveraging more digital equalization whose efficiency improves with each technology generation.Broader Impact: The explosion in interconnect bandwidth capacity provided by this converter-based serial link architecture will allow the realization of numerous transformative applications, such as future smart mobile devices capable of Tflop/s performance, multi-channel high-resolution magnetic resonance imaging, and exascale supercomputers necessary for climate modeling and protein folding simulations. Interconnect architectures developed with the proposed optimization framework will have a broad impact on not only the semiconductor industry, but also on the sustainability and security of the nation as a whole, as it will dramatically reduce the energy these integrated systems demand. This project will include an interdisciplinary educational program involving 2 Ph.D. and 3 undergraduate students, with a commitment in several engaging outreach activities to foster the representation of women and minority groups. Project results will be broadly disseminated by inclusion in the syllabi and website of the graduate course entitled "High-Speed Links Circuits and Systems" and through publication in national and international journals and conferences.