CAREER: Process, Voltage, and Temperature (PVT)-Tolerant CMOS Photonic Interconnect Transceiver Architectures

智力优势：本文提出的光子互连架构和设计技术旨在显著提高互连鲁棒性、能量效率和带宽密度，这是未来计算机系统持续扩展所必需的。虽然在光子互连方面取得了进展，但最有效地利用这些光器件进行片外和片上网络应用的最佳互连架构仍然是一个悬而未决的问题。这个工作吗?S的研究目标是开发基于集成环形谐振器调制器和波导光电探测器的统一片间和片内光子互连架构的鲁棒节能收发器。为了实现这一目标，将开发一个用于光子片上网络和芯片间链路的超快速系统级优化框架，该框架将研究带宽密度、能量效率和互连吞吐量的权衡，以比较光子互连技术，并在拟议架构的设计中加以利用。新的电路拓扑结构将被开发，以解决由于纳米晶体管缩放特性所带来的挑战，例如晶体管可靠性限制与光源器件的电压摆幅要求相冲突，晶体管增益缩小和不匹配增加对接收器灵敏度有很大影响。系统级优化与电路级精度和新的超高效电路拓扑相结合，使架构能够利用光子互连？极低延迟和高带宽的特性，以实现具有数量级性能改进的全新计算模型。更广泛的影响：这种光子互连架构提供的互连带宽容量的爆炸式增长将使许多变革性应用得以实现，例如未来能够实现Tflop/s性能的智能移动设备、多通道高分辨率磁共振成像和百亿亿次超级计算机。根据提出的优化框架开发的互连架构不仅将对美国半导体行业产生广泛影响，而且还将对整个国家的可持续性和安全性产生广泛影响，因为它将大大减少这些集成系统的能源需求。该项目将包括一个跨学科的教育项目，涉及1名博士和5名本科生，并承诺开展几项引人入胜的外展活动，以促进妇女和少数群体的代表性。这些活动包括为K-12学校教师参加为期四周的暑期讲习班，以及每年为高中生举办为期一周的夏令营。项目成果将被广泛传播，包括在一门名为？光互连电路和系统？并通过在国内和国际期刊和会议上发表文章。

Intellectual Merit: The photonic interconnect architectures and design techniques proposed here aim to significantly improve interconnect robustness, energy efficiency, and bandwidth density, which is necessary for continued scaling of future computer systems. While progress has been made in photonic interconnects, the optimal interconnect architecture which most efficiently leverages these optical devices for off-chip and network-on-chip applications is still an open question. This work?s research goal is to develop robust energy-efficient transceivers for a unified inter- and intra-chip photonic interconnect architecture based on integrated ring resonator modulators and waveguide photodetectors. To accomplish this goal, an ultra-fast system-level optimization framework for photonic on-chip networks and inter-chip links that investigates trade-offs in bandwidth density, energy efficiency, and interconnect throughput will be developed to compare photonic interconnect technologies and leveraged in the design of the proposed architecture. Novel circuit topologies will be developed that address challenges imposed due to nanometer transistor scaling properties, such as transistor reliability constraints conflicting with voltage-swing requirements of optical source devices and shrinking transistor gain and growing mismatch having a large impact on receiver sensitivity. The combination of system level optimization with circuit-level accuracy and new ultra-efficient circuit topologies enables architectures capable of leveraging photonic interconnects? properties of extreme low latency and high bandwidth to realize completely new computing models with orders of magnitude performance improvement.Broader Impact: The explosion in interconnect bandwidth capacity provided by this photonic interconnect architecture will allow the realization of numerous transformative applications, such as future smart mobile devices capable of Tflop/s performance, multi-channel high-resolution magnetic resonance imaging, and exascale supercomputers. Interconnect architectures developed with the proposed optimization framework will have a broad impact on not only the US semiconductor industry, but also on the sustainability and security of the nation as a whole, as it will dramatically reduce the energy these integrated systems demand. This project will include an interdisciplinary educational program involving 1 Ph.D. and 5 undergraduate students, with a commitment in several engaging outreach activities to foster the representation of women and minority groups. These activities include participating in a four-week summer workshop for K-12 school teachers and also annual one-week summer camps for high school students. Project results will be broadly disseminated by inclusion in the syllabi and website of a new graduate course entitled ?Optical Interconnect Circuits and Systems? and through publication in national and international journals and conferences.