ACED Fab: Co-Design of Novel Electronic-Photonic Systems for Energy-Efficient Coherent Optical Interconnects
ACED Fab: Co-Design of Novel Electronic-Photonic Systems for Energy-Efficient Coherent Optical Interconnects
批准号:
2314868
负责人:
Samuel Palermo
金额:
$40.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2023
资助国家:
美国
项目状态:
未结题
起止时间:
2023-07-01 至 2026-06-30
中文摘要
为了支持机器学习、人工智能、传感器系统和5G/6G工作负载的进步,数据中心和高性能计算系统的互连带宽密度和能源效率的大幅提高是必要的。然而,在传统的强度调制直接检测(IMDD)光链路中,由于极高的波特率(即每秒信号的变化),扩展数据速率存在基本限制。相干光互连提供了一个潜在的解决方案,因为它们可以调制光载波的振幅和相位,并利用双偏振(DP)操作来允许每个波长的带宽密度急剧增加。虽然相干光链路具有频谱效率,但主要挑战包括有限的硅光子调制器带宽,由于光子器件和前端电路的独立设计而导致的高功率收发器,对光子器件制造变化的敏感性,以及通常在复杂数字信号处理器(DSP)块中执行的高功率接收端光载波恢复。该提案通过共同设计高带宽光子器件和先进节点CMOS前端来解决这些重要问题,这些前端可以适应光学器件性能的变化,并利用基于双环光锁相环(OPLL)的节能接收端载波恢复方案。该技术将实现高能效的相干光收发器,从而实现数据中心流量容量的大幅扩展,以支持由联网汽车等新兴应用驱动的网络设备的前所未有的增长。本提案的研究目标是开发一种相干光学互连体系结构,该体系结构采用薄膜LiNbO3 (TF-LN)马赫-曾德尔调制器(MZMs)和石墨烯光电探测器的正交解调器,具有新型高带宽正交调制器。为了实现这一目标,我们将共同设计具有动态电压频率缩放(DVFS)和高效开关调节器的节能CMOS发射器,以及具有DVFS、自适应带宽前端和自调谐正交解调器的节能CMOS接收器。此外,还将开发一种基于光学锁相环(OPLL)的宽范围电子压控振荡器(VCO)调谐载波恢复方案。由于该技术能够提供无错误编码的低延迟互连,因此应用该技术将彻底改变数据中心和高性能计算系统的未来。该项目将由2名德州农工大学(TAMU)学生和3-4名国立中兴大学(NCHU)学生组成的跨学科团队参与。两套原型将采用两种先进的CMOS工艺,一种硅光子工艺和定制的薄膜TF-LN集成电路来实现。项目外展活动包括交流和访问活动,TAMU和NCHU的学生在关键的IC设计阶段面对面地在现场工作,还参加联合研讨会,通过工程丰富经验(E3)计划与高中教师互动,并通过Spark!程序。项目成果将广泛传播,包括列入题为“相干光学系统”的新研究生课程的教学大纲和网站,为学术界和工业界开发在线模块,并通过在国家和国际期刊和会议上发表。该奖项反映了美国国家科学基金会的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Dramatic improvements in datacenters and high-performance computing systems’ interconnect bandwidth-density and energy-efficiency are necessary to support advances in machine learning, artificial intelligence, sensor systems, and 5G/6G workloads. However, there are fundamental limitations to scaling data rates in conventional intensity-modulated direct detection (IMDD) optical links due to the extreme baud rates, i.e. changes in signals per second. Coherent optical interconnects offer a potential solution, as they modulate both the amplitude and phase of the optical carrier and utilize dual polarization (DP) operation to allow for a dramatic increase in bandwidth-density per wavelength. While coherent optical links are spectrally-efficient, key challenges include limited silicon photonic modulator bandwidth, high-power transceivers due to independent design of the photonic devices and front-end circuitry, sensitivity to photonic device fabrication variations, and high-power receiver-side optical carrier recovery that is commonly performed in a complex digital signal processor (DSP) block. This proposal addresses these important issues by co-designing high-bandwidth photonic devices and advanced-node CMOS front-ends that can adapt to variations in optical device performance and by utilizing a power-efficient receive-side carrier recovery scheme based on a dual-loop optical phased-locked loop (OPLL). The proposed technology will enable energy efficient coherent optical transceivers that will allow dramatic scaling in datacenter traffic capacity to support the unprecedented growth in networked devices driven by emerging applications such as connected automobiles, for example. This proposal’s research goal is to develop a coherent optical interconnect architecture with novel high-bandwidth quadrature modulators with thin-film LiNbO3 (TF-LN) Mach-Zehnder modulators (MZMs) and quadrature demodulators with graphene photodetectors. Co-design of energy-efficient CMOS transmitters with dynamic voltage frequency scaling (DVFS) with efficient switching regulators and energy-efficient CMOS receivers with DVFS, adaptive bandwidth front-ends, and auto-tuned quadrature demodulators will be fabricated to accomplish this goal. In addition, an optical phase-locked loop (OPLL) based carrier recovery scheme with wide-range electronic voltage-controlled oscillator (VCO) tuning will be developed. Applying the proposed technology will revolutionize the future of both datacenter and high-performance computing systems due to its ability to offer low-latency interconnects without error coding. This project will involve an interdisciplinary team of 2 Texas A&M University (TAMU) students and 3-4 National Chung Hsing University (NCHU) students. Two sets of prototypes will be implemented using two advanced CMOS processes, a silicon photonic process, and custom-fabricated thin-film TF-LN integrated circuits. Project outreach activities include exchange and visiting activities where TAMU and NCHU students work together face-to-face on-site during critical IC design phases and also participate in joint workshops, interactions with high school teachers via the Enrichment Experiences in Engineering (E3) program and introducing basic research concepts to PK-12 students through the Spark! Program. Project results will be broadly disseminated by inclusion in the syllabus and website of a new graduate course entitled "Coherent Optical Systems", the development of online modules for academia and industry, and through publication in national and international journals and conferences.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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EARS: A Wideband Frequency-Agile Silicon Photonic mm-Wave Receiver with Automatic Jammer Suppression via Rapidly Reconfigurable Optical Notch Filters
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批准号:1547432
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项目类别:Standard Grant
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资助金额:$62.5万
-
财政年份:2015
-
负责人:Samuel Palermo
-
依托单位:
CAREER: Process, Voltage, and Temperature (PVT)-Tolerant CMOS Photonic Interconnect Transceiver Architectures
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批准号:1254830
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项目类别:Standard Grant
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资助金额:$40.0万
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财政年份:2013
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负责人:Samuel Palermo
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依托单位:
Advanced Modeling and Design of High-Performance ADC-Based Serial Links
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批准号:1202508
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项目类别:Standard Grant
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资助金额:$36.0万
-
财政年份:2012
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负责人:Samuel Palermo
-
依托单位:
国内基金
海外基金
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