SBIR Phase I: On Demand Verification for Analog Integrated Circuits

该小型企业创新研究第一阶段项目建议为模拟/混合信号应用(A/MS)专用集成电路(ASIC)提供按需验证(ODV)设施。该技术创新是一个基于云的虚拟验证平台，支持集成电路设计中心A/MS ASIC验证的方方面面，包括行为建模、测试台管理、模拟规划、模拟耕种和数据挖掘。建议的ODV系统可根据ASIC的复杂性进行扩展，并通过利用云计算资源扩展设计人员。更重要的是，一旦完成验证任务，建议的验证资源就可以缩减，为小型设计中心创造机会，为设计运营创造具有竞争力的成本结构的高质量设计。最初的概念验证设计系统将配备开源的EDA设计、建模和验证软件工具。建议的验证平台固有的模块化还将支持ODV设施的订户安装一流的商业合作伙伴软件解决方案，并将其用于ASIC验证活动。该项目的更广泛影响/商业潜力是通过缩短A/MS设计验证周期、提高首次通过设计成功率和缩短上市时间来提高美国半导体行业的竞争力。A/MS ASIC设计的复杂性遵循摩尔-S定律，而设计验证的创新却不是这样。鉴于现有的EDA许可模式，小型、无厂房的模拟设计中心在复杂的设计创作方面尤其难以竞争。例如，为一个小型设计团队配备适当的验证和分析工具，在财务上相当于将工作人员增加四倍。这项研究工作的结果将通过提供可扩展的验证服务来降低小型和新兴公司的进入和创新门槛，而不会产生额外的软件许可成本和基础设施管理费用的繁重负担。此外，ODV系统通过基于云的平台实现了市场参与者之间的更多协作创新。这将使现有的半导体市场参与者大大受益，并为新的参与者打开大门。

This Small Business Innovation Research Phase I project proposes an on-demand verification (ODV) facility for analog / mixed-signal application (A/MS) specific integrated circuits (ASICs). The technology innovation is a virtualized cloud-based verification platform that supports all aspects of A/MS ASIC verification for integrated circuit design centers, including behavioral modeling, test bench management, simulation planning, simulation farming, and data mining. The proposed ODV system scales with ASIC complexity and design staff expansion by leveraging cloud computing resources. More importantly, the proposed verification resources can be scaled down once verification tasks are complete, creating opportunities for small design centers to create high quality designs with competitive cost structure for design operations. The initial proof-of-concept design system will be equipped with open source EDA design, modeling, and verification software tools. The modularity inherent in the proposed verification platform will also support the installation of best-in-class commercial partner software solutions and their use in ASIC verification activities by subscribers to the ODV facility.The broader impact/commercial potential of this project is to improve the competitiveness of U.S. semiconductor industry by reducing A/MS design verification cycle time, improving first pass design success and reducing time-to-market. The complexity of A/MS ASIC design has aggressively followed Moore?s law, but innovations in design verification have not. Small, fabless analog design centers in particular struggle to compete in complex design creation given the existing EDA licensing model. Equipping a small design team with the proper verification and analysis tools, for example, is financially equivalent to quadrupling the staff. The results of this research work will lower barriers to entry and innovation for small and emerging companies by providing a scalable verification service without the onerous burden of additional software licensing costs and infrastructure overhead. In addition, the ODV system enables more collaborative innovation among the market players through a cloud-based platform. This would materially benefit the existing semiconductor market participants and open the door for new participants.