CSR: Small: Memory-Centric Real-Time Scheduling for Multicore Embedded Systems

在现代汽车和航空电子应用中，使用多个传感器，特别是实时成像传感器会产生前所未有的工作量。从计算的角度来看，多核架构已经成为主流；然而，随着多核芯片需要实时处理越来越多的数据量，内存层次结构成为瓶颈资源。在最坏的情况下，任务执行时间可能会随着系统中的核心数量线性增长。本研究旨在为现代以内存为中心的实时调度理论奠定基础，该理论可以有效地协同调度内存层次、内核和片上网络（包括I/O通道）的使用。根据内存中心调度的观点，当内存层次结构是系统瓶颈时，应该调度内存访问以实现高内存利用率。实时多核系统的性能应该根据可调度内存利用率来衡量，而不仅仅是根据核心利用率来衡量。理想情况下，只要所有实时应用程序（跨所有争用共享内存的核心）的总内存利用率低于100%，就应该满足实时约束。这项研究的潜在经济和社会效益是显著的，因为发展的理论将大大增加嵌入式多核软件系统的时间可预测性，同时特别是降低实现下一代航空电子多核计算架构必要的安全认证所需的成本和时间。随着新的调度理论的发展，关键要素将被纳入实时计算的研究生课程，然后转移到大四的本科课程。

In modern automotive and avionics applications, the use of multiple sensors and especially real-time imaging sensors creates unprecedented workloads. From a computational perspective, multicore architectures have become mainstream; however, as a multicore chip is expected to process increasing volumes of data in real-time, the memory hierarchy becomes the bottleneck resource. In the worst case, task execution times can grow linearly with the number of cores in the system. This research aims at laying foundations for a modern memory-centric real-time scheduling theory that can effectively co-schedule the use of the memory hierarchy, the cores, and the on-chip network, including the I/O channels. According to the vision of Memory-Centric Scheduling, when the memory hierarchy is the system bottleneck, memory accesses should be scheduled to achieve high memory utilization. Performance of a real-time multicore system should be measured in terms of schedulable memory utilization rather than just core utilization. Ideally, the real-time constraints should be met as long as total memory utilization of all real-time applications (across all the cores contending for shared memory) is below 100%.The potential economic and social benefits of this research are significant since the developed theory will greatly increase the temporal predictability of embedded multicore software systems in general, while in particular reducing cost and time required to achieve the necessary safety certification of next generation avionic multicore computing architectures. As the new scheduling theory is being developed, key elements will be incorporated into graduate classes in real-time computing and then migrated to senior undergraduate classes.