TWC: Phase: Medium: Collaborative Proposal: Understanding and Exploiting Parallelism in Deep Packet Inspection on Concurrent Architectures

深度包检测（DPI）是保护网络免受新兴和复杂攻击的重要工具。然而，由于对更复杂分析的需求不断增加，再加上这些系统必须检查的网络流量不断增长，有效实施DPI变得越来越困难。为了应对这一挑战，未来的DPI技术必须充分利用新兴的高并发多核和多核平台的强大功能。然而，不幸的是，当前的DPI系统严重限制了它们对并行性的使用，要么采用粗粒度负载平衡，要么将它们的分析限制在非常简单的硬编码检测器上。为了充分利用并行硬件平台，在这个项目中，我们开发了一种全面的方法，在复杂的DPI管道的所有阶段引入并行性。我们研究了独立于应用程序的调度策略，该策略采用现有的DPI分析并自动并行化其处理。我们通过将它们映射到特定于领域的中介表示来实现这一点，该中介表示从底层硬件架构的细节中抽象出来，同时提供低级一致性保证。从概念上讲，该项目的目标是将并行性虚拟化和抽象为基本的原语，就像虚拟内存从程序员那里抽象出物理内存大小的限制一样。

Deep packet inspection (DPI) is a crucial tool for protecting networks from emerging and sophisticated attacks. However, it is becoming increasingly difficult to implement DPI effectively due to the rising need for more complex analysis, combined with the relentless growth in the volume of network traffic that these systems must inspect. To address this challenge, future DPI technologies must exploit the power of emerging highly concurrent multi- and many-core platforms. Unfortunately, however, current DPI systems severely limit their use of parallelism by either resorting to coarse-grained load-balancing or restricting their analysis to very simple, hard-coded detectors.In order to fully exploit parallel hardware platforms, in this project we develop a comprehensive approach that introduces parallelism across all stages of the complex DPI pipeline. We investigate application-independent scheduling strategies that take existing DPI analyses and automatically parallelize their processing. We do so by mapping them into a domain-specific intermediary representation that abstracts from specifics of the underlying hardware architecture while providing low-level consistency guarantees. Conceptually, the project's goal is to virtualize and abstract parallelism as a fundamental primitive, just like how virtual memory abstracts away physical memory size limitations from programmers.