Design Automation for Cost-Effective Implementation of Adaptive Integrated Circuits

变化性是阻碍半导体技术进步的重大挑战。自适应设计被认为是解决这一挑战的一种有前途的方法，特别是在芯片功耗限制日益严格的情况下。然而，它在实践中的应用是有限的，主要是因为缺乏系统的技术来管理其开销、复杂性以及与现有设计流程的集成。这项研究将开发一个设计自动化框架，以优化适应性资源的使用，最大化其效率，并平衡与传统设计目标的权衡。这项研究的关键是以一种轻量级的方式捕捉适应性设计的不确定性和动态性，但又要高保真。将结合稳健的优化方法研究新的可变性和适应性模型。此外，还将研究一种正式的技术，以处理相互竞争的设计目标之间的权衡。还将探索并行计算技术，以应对当前和新兴应用程序的巨大问题规模。这项研究将加强自适应电路技术中的一些薄弱环节，为其广泛应用铺平道路。它将同时解决纳米半导体技术面临的变化性和功率挑战。芯片能效的潜在提高将促进绿色计算技术的发展。此外，建议的技术将适用于下一代器件技术，因此将有利于半导体行业的未来。这项研究也将作为一个试验台，训练学生了解现代芯片设计过程的各个方面之间的协同效应。

Variability is a grand challenge that hinders the progress of semiconductor technology. Adaptive design is considered a promising approach for addressing this challenge, especially under increasingly tight chip power constraints. However, its application in practice is limited, largely due to the lack of systematic techniques for managing its overhead, complexity, and integration with existing design flows. This research will develop a design automation framework that optimizes the use of adaptivity resources, maximizes their efficiency, and balances the tradeoff with conventional design objectives. The key of this research is capturing the uncertainty and dynamics of adaptive designs in a lightweight manner, yet with high fidelity. New variability and adaptivity models will be investigated in conjunction with robust optimization methods. In addition, a formal technique will be studied to handle the tradeoffs among competing design objectives. Parallel computing techniques will also be explored to cope with the enormous problem sizes of current and emerging applications. This research will strengthen some weak links in adaptive circuit technology and help pave a path toward its wide applications. It will simultaneously address variability and power challenges faced by nanometer semiconductor technologies. The potential improvement of chip power-efficiency will facilitate green computing technology. Furthermore, the proposed techniques will be applicable to next-generation device technologies and will therefore benefit the future of the semiconductor industry. This research will also serve as a test-bed for training students to understand synergies among various aspects of modern chip design processes.