SHF: Small: Collaborative Research: Variation-Resilient VLSI Systems with Cross-Layer Controlled Approximation

通过人类五种感官进行人机交互所驱动的应用程序预计将成为下一代计算的基础。对于这些应用中的许多应用，偶尔的小错误不仅是可以接受的，而且还带来了构建更轻、更便宜、更强大的系统的机会，这些系统使用更少的能源，并且可能具有更长的电池寿命。这个项目将研究如何通过近似计算的概念在硬件实现中允许故意不精确，从而推动计算技术的发展。该项目的成果将是一套近似计算的设计技术，可以成为硬件计算技术的关键组件，可能使大数据分析的高性能计算和物联网的低功耗实施等系统受益。该项目还将为培训学生掌握最新的设计和计算技术提供机会。该项目的研究目标是创建新的近似计算技术，以在系统生命周期的所有阶段(从设计时到运行时)进行优化，从而实现对性能-功率-精度权衡的跨层控制。研究议程由几个部分组成。首先，将开发具有不同精度-复杂性权衡的新的误差模型。其次，将研究新的设计时优化技术，特别是高级综合中的硬件资源调度和绑定，并考虑近似、变异和运行时电路重构。第三，将研究编译时和操作系统级任务映射/调度算法，以充分利用各种精度的电路。最后但并非最不重要的一点是，我们将结合动态电压和频率调节来探索运行时精确控制技术，以便在功率和用户体验之间实现平稳的平衡。

Applications driven by human-computer interactions through the five human senses are projected to underpin the next generation of computing. For many of these applications, occasional small errors are often not only acceptable but also bring opportunities for building lighter, cheaper, and more robust systems that use less energy and may have a longer battery life. This project will study how to advance computing technology by allowing deliberate imprecision in hardware implementations through the notion of approximate computing. The outcomes of this project will be a set of design techniques for approximate computing that can become a key component of hardware computing technology, potentially benefiting systems ranging from high performance computing for big data analytics and low power implementation for internet of things. This project will also provide an opportunity for training students with the latest design and computing technology. The research goals of this project are to create new approximate computing techniques to optimize a system at all stages of its life, from design-time to runtime, which can enable cross-layer control of performance-power-precision trade-offs. The research agenda consists of several components. First, new error models with different accuracy-complexity trade-offs will be developed. Second, new design-time optimization techniques, especially hardware resource scheduling and binding in high-level synthesis, will be studied with consideration of approximation, variation, and runtime circuit reconfiguration. Third, compile-time and operating-system-level task mapping/scheduling algorithms will be investigated to make the best use of circuits with various precisions. Last but not least, runtime precision control techniques will be explored in conjunction with dynamic voltage and frequency scaling in order to achieve a smooth trade-off between power and user experience.