Collaborative Research: SHF: Medium: Automated energy-efficient sensor data winnowing using native analog processing

协作研究：SHF：中：使用本机模拟处理进行自动节能传感器数据筛选

• 批准号: 2212346
• 负责人: Jiang Hu
• 金额: $ 30万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2212346&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Medium; Automated

As computing becomes pervasive in all aspects of daily life, computing hardware must allow for increasing interaction with the physical world. This interaction takes the form of sensed signals that are analog in nature, e.g., a sensor may output a voltage that can take on a continuous range of values. Traditional mainstream computing digitizes this data, converting it to digital 0s and 1s for efficient analysis and processing. However, as the amount of sensed analog data is growing exponentially, digital processors will be faced with a data deluge from external sensors. For these vast volumes of data, even the cost of converting analog input data to digital signals, prior to any processing, can be prohibitively expensive. Native analog processing (NAP) negates the need for analog-to-digital conversion by working in the analog domain. NAP can be used to implement data processing functions inexpensively, but can achieve only limited accuracy; on the other hand, digital processing can achieve high accuracy, but requires the overhead of analog-to-digital conversion. This project presents a methodology for mixed-signal processing that hybridizes digital and analog subcircuit implementations to achieve the best of both worlds. The effort intends to actively engage with the semiconductor industry, and will train graduate and undergraduate students in the area of semiconductor design, thus alleviating the national skills shortage in this area.In the first step, computing tasks are automatically partitioned into hybrid analog/digital segments, with the goal of meeting system-level constraints on throughput, power, and noise/error. The computations associated with a task are abstractly represented by a dataflow graph (DFG). This representation is widely used to model a variety of tasks, including those commonly used in digital signal processing and machine learning. The nodes in the DFG are mapped to analog or digital implementations, using cost functions that represent the cost of implementation, as well as the cost of any required analog-to-digital or digital-to-analog conversion. Next, the analog and digital circuitry is optimized to build a silicon implementation at the layout level, based on cutting-edge transistor technologies, which involve restrictive design rules that impose limitations such as unidirectional routing and gridded layout. The optimizations are facilitated by novel techniques for back-end analysis, synthesis, and implementation developed in this project, including transistor and interconnect optimizations, placement and routing techniques that are specifically targeted to mixed-signal designs, and compact performance machine-learning-based model generation that efficiently predicts circuit performance. The project thus automatically translates the system-level DFG specification of a computing task to an optimized mixed-signal silicon implementation.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

随着计算在日常生活的各个方面变得普遍，计算硬件必须允许增加与物理世界的交互。这种相互作用以感知信号的形式存在，这些信号本质上是模拟的，例如，传感器可以输出一个可以取连续范围值的电压。传统的主流计算将这些数据数字化，将其转换为数字0和1，以进行有效的分析和处理。然而，随着感测模拟数据量呈指数级增长，数字处理器将面临来自外部传感器的数据泛滥。对于这些庞大的数据量，甚至在任何处理之前将模拟输入数据转换为数字信号的成本都可能非常昂贵。原生模拟处理（NAP）通过在模拟域中工作，否定了模数转换的需要。NAP可用于实现低成本的数据处理功能，但只能达到有限的精度；另一方面，数字处理可以达到较高的精度，但需要模数转换的开销。本项目提出了一种混合信号处理方法，该方法混合了数字和模拟子电路的实现，以实现两全其美。该计划旨在积极参与半导体行业，并将培养半导体设计领域的研究生和本科生，从而缓解该领域的国家技能短缺。在第一步中，计算任务被自动划分为混合模拟/数字段，目标是满足吞吐量、功率和噪声/错误的系统级约束。与任务相关的计算用数据流图（DFG）抽象地表示。这种表示被广泛用于各种任务的建模，包括那些在数字信号处理和机器学习中常用的任务。DFG中的节点被映射到模拟或数字实现，使用表示实现成本的成本函数，以及任何所需的模数或数模转换的成本。接下来，基于尖端晶体管技术，优化模拟和数字电路，以构建布局级的硅实现，其中涉及限制性设计规则，施加单向路由和网格布局等限制。该项目开发的后端分析、综合和实现的新技术促进了优化，包括晶体管和互连优化、专门针对混合信号设计的放置和路由技术，以及高效预测电路性能的基于机器学习的紧凑性能模型生成。因此，该项目自动将计算任务的系统级DFG规范转换为优化的混合信号硅实现。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Performance-driven Wire Sizing for Analog Integrated Circuits

• DOI: 10.1145/3559542
• 发表时间: 2022-08
• 期刊: ACM Transactions on Design Automation of Electronic Systems
• 影响因子: 1.4
• 作者: Yaguang Li;Yishuang Lin;Meghna Madhusudan;A. Sharma;S. Sapatnekar;R. Harjani;Jiang Hu