EAGER: Collaborative Research: Characterizing Microarchitectural Mechanisms for Network Delay Signatures

随着半导体技术的进步以及计算机网络的速度和可靠性的提高，计算和通信之间的区别变得模糊了。在宏观层面，个人越来越依赖智能手机、云计算和类似的基础设施，这些基础设施将计算系统与网络相结合来完成他们的日常任务。从计算系统和网络的无缝互连中实现优势。许多最终用户甚至将客户端设备、服务器和网络视为一个用于工作和/或娱乐的单元。在微观层面上，当计算和网络融合时，类似的效率也会显现出来。在理想情况下，这两个区域之间的链接应该不需要使用特殊用途的软件，因为在网络节点上安装软件以实现这种混合可能会导致节点不稳定、更复杂，并引入安全缺陷。然而，在不使用额外软件的情况下将这两个域连接起来是一个巨大的挑战。这项研究的重点是理解和刻画计算节点和网络之间的连接。由于节点的内部组件是所有进程之间的共享资源，包括那些需要基于网络的I/O的进程，因此可以通过观察节点生成的连续网络数据包之间的延迟变化来推断内部组件上的负载。这种推论体现为“延迟签名”，可用于混合体系结构和网络领域。具体地说，这些信息可用于开发网络安全和管理算法。例如，通过简单地探测节点并收集其响应，可以确定内部组件(例如微处理器)被大量使用。如果预计该节点处于空闲状态，这可能表示该节点已遭到破坏，并且正在运行未经授权的软件。该信息还可用于集群网格中的作业调度。通过监测网格节点之间的消息传递接口(MPI)消息，无需直接查询节点即可确定节点上的负载。因此，不需要资源发现消息。此信息的另一个用途可以是预测系统降级和故障。当节点的资源耗尽时，该节点会生成唯一的流量模式。此模式在节点故障之前发出，可用于向辅助服务器发出切换信号。该项目使用计算机体系结构和计算机网络相结合的整体方法来调查和表征微体系结构如何影响网络数据包生成过程。延迟签名提供可归因于微体系结构的内部状态和设置的信息。架构设置(如处理器亲和性、多线程和节能模式)会影响延迟签名。PI使用硬件试验台和系统模拟器来表征微处理器内的基本机制，这些基本机制体现在可观察到的延迟签名中。研究人员将以团队为基础的实验室项目纳入其计算机体系结构和计算机网络课程，以演示这两个领域之间的关系，并促进学生在这两个领域的综合学习。延迟签名的潜在应用包括通过监视未经授权的使用来为联网的节点提供安全性，以及通过检测预测节点故障的模式来增加计算系统的弹性。

The distinction between computing and communication has blurred with the improvements in semiconductor technology as well as the speed and reliability of computer networks. At a macroscopic level, individuals increasingly rely upon smart phones, cloud computing, and similar infrastructure that combines computing systems with networking to accomplish their daily tasks. Advantages are realized from the seamless interconnection of computing systems and the network. Many end-users even consider the client device, the server, and the network as one unit that is used for productivity and/or entertainment. At the microscopic level, similar efficiencies present themselves when computing and networking blend. In an ideal case, the linkage between the two areas should not require the use of special-purpose software, because installing software on a network node to enable this blending can potentially cause the node to be unstable, more complex, and introduce security flaws. However, there is a significant challenge in linking the two domains without the use of additional software. This research focuses on understanding and characterizing the connection between the computing node and the network. Since the internal components of a node are shared resources between all processes, including those that require network-based I/O, it is possible to infer the load on the internal components by observing variations in delay between successive network packets that are generated by the node. This inference materializes as a "delay signature," and can be used to blend the areas of architecture and networking. Specifically, this information can be used to develop algorithms for network security and management. For example, by simply probing a node and collecting its responses, it can be determined that the internal components (e.g., microprocessor) are heavily utilized. If the node is expected to be idle, this could be an indication that the node has been compromised and is running unauthorized software. This information can also be used for job scheduling in cluster grids. By monitoring Message Passing Interface (MPI) messages between grid nodes, the loads on the nodes can be determined without querying nodes directly. As a result, resource discovery messages are not needed. Another use of this information can be to predict system degradation and failure. As a node's resources become exhausted, the node generates a unique traffic pattern. This pattern is emitted prior to node failure and can be used to signal a switch to a secondary server.This project uses a holistic approach that combines computer architecture and computer networking to investigate and characterize how the microarchitecture affects the network packet generation process. The delay signature provides information that can be attributed to the internal state and settings of the microarchitecture. Architectural settings, such as processor affinity, multi-threading, and power-saving modes, affect the delay signature. The PIs use a hardware testbed and a system simulator to characterize the basic mechanisms within the microprocessor that are manifested in the observable delay signature. The investigators incorporate team-based laboratory projects within their computer architecture and computer networking courses to demonstrate the relationship between the two domains and to promote integrated learning by students in both areas. Potential applications of the delay signature include providing security for networked nodes by monitoring unauthorized utilization and increasing resiliency of a computing system by detecting patterns that predict a node failure.