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Collaborative Research: From High-level Synthesis to Layout: a Cross-layer Methodology for Large-scale Reliable IC Design

Collaborative Research: From High-level Synthesis to Layout: a Cross-layer Methodology for Large-scale Reliable IC Design
协作研究:从高级综合到布局:大规模可靠IC设计的跨层方法
批准号:
1255816
负责人:
David Pan
金额:
$10.5万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2013
资助国家:
美国
项目状态:
已结题
起止时间:
2013-04-01 至 2017-03-31

项目摘要

项目成果

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中文摘要
翻译
设计具有高设计生产率的鲁棒且节能的大规模片上系统(SOC)是一个非常有趣的挑战。然而,不同设计层之间缺乏协调已经导致设计者在各个设计层处做出最坏情况的假设,从而导致具有差的可靠性/能量/性能协同优化或权衡的基本上次优的设计。该项目是第一个致力于从高层次综合到紧密集成的物理设计的统一抗故障系统的重大努力。它将建立以可靠性为中心的物理感知的高层次综合和高层次指导的物理设计,以弥合这两个遥远的层之间的差距。一个新的跨层工程变更单(ECO)框架也将被开发耦合高层次的ECO与稳定的物理级ECO。将研究新的工具和方法,并提供给系统和物理设计界,以提高可靠性,同时提高总体设计生产力和质量。电子技术已经渗透到现代社会,现代社会越来越依赖于这些电子系统的可靠运行。然而,设备级扩展正朝着与系统可靠性相反的方向发展。该项目将通过跨层集成改造现有的SOC设计方法。这项工作的研究将通过出版物和演示文稿,与工业合作者的积极互动以及将新课程材料注入教室和教学实验室来广泛传播。主要研究人员将继续努力招募妇女和其他代表性不足的少数民族参加他们的研究计划。他们以前已经接触到K-12学生,并将继续这样做,以吸引他们中最好的进入工程专业。
英文摘要
Designing robust and energy-efficient large-scale systems-on-chips (SOCs) with high design productivity is a challenge of great interest. However, lack of coordination among different design layers has caused designers to make worst-case assumptions at individual design layers, leading to substantially suboptimal designs with poor reliability/energy/performance co-optimization or tradeoffs. This project is the first major effort dedicated toward a unified failure-resistant system from high-level synthesis to physical design with tight integration. It will build reliability-centric physical-aware high-level synthesis and high-level-guided physical design to bridge the gap between these two distant layers. A novel cross-layer engineering change order (ECO) framework will also be developed to couple high-level ECO with stable physical-level ECO. New tools and methodologies will be studied and provided to the system and physical design community targeting reliability while increasing overall design productivity and quality. Electronics have permeated modern society, which increasingly depends on reliable operations of these electronic systems. However, device-level scaling is heading in the opposite direction from system reliability. This project will transform existing SOC design methodologies through cross-layer integration. Research from this effort will be broadly disseminated through publications and presentations, active interaction with industrial collaborators, as well as infusion of new course material into classrooms and instructional laboratories. The principal investigators will continue their efforts in recruiting women and other underrepresented minorities into their research programs. They have previously reached out to K-12 students and will continue to do so in order to attract the best of them into the engineering profession.
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Collaborative Research: SaTC: CORE: Medium: Security and Robustness for Intermittent Computing Using Cross-Layer Post-CMOS Approaches
  • 批准号:
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  • 项目类别:
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  • 资助金额:
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  • 财政年份:
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SHF: Medium: Integrating Human and Machine Intelligence for Next Generation Interactive Analog IC Design
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  • 资助金额:
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SHF: Small: Design/Technology Co-Optimization and Exploration in Emerging Scaling
  • 批准号:
    1718570
  • 项目类别:
    Standard Grant
  • 资助金额:
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SHF: SMALL: GOALI: Design for Manufacturability in Extreme Scaling with Emerging Nanolithography
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    1218906
  • 项目类别:
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  • 资助金额:
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  • 财政年份:
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  • 负责人:
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