CAREER: A Synergistic CAD Framework for Nanometer Design and Process Integration

提案ID：0644316职务：职业：纳米设计和工艺集成的协同CAD框架PI：大卫潘机构：UT奥斯汀摘要：经过四十年的摩尔定律授权的CMOS缩放，半导体行业正面临着前所未有的设计和制造挑战。该行业仍然坚持193 nm光刻作为主要的集成电路制造工艺，对于45 nm，32 nm甚至22 nm技术节点，这种情况可能会持续至少5年。深亚波长光刻的一个显著特点是其邻近性、布局依赖性效应。据估计，在纳米设计中，光刻和设计相关的成品率损失可能占总成品率损失的80%或更多。然而，它并没有很好地捕捉到现有的设计流程，从建模到优化。该项目将开发一个协同计算机辅助设计（CAD）框架，使整体设计和过程集成。 它将通过开发一套面向设计但具有变化意识的制造/产量模型，以及使用预测虚拟硅图像的几何和电气特性，来解决产量损失的根本原因。因此，它将有助于消除产量分析和优化的显着数量的不确定性。同时，在建模框架的指导下，新的CAD算法将在不同的抽象层次和架构的探索将进行多目标的设计/制造优化。该项目将进一步研究纳米光刻和混合CMOS/post-CMOS工艺等新兴技术的设计和工艺集成问题。该项目的综合教育部分将在这一高度交叉和重要的领域培养多样化的学生，电路设计，CAD和制造的交叉和共同发展为学生接触多个工程学科创造了绝佳的机会。综合考虑，该项目旨在填补设计/CAD和制造/工艺之间的关键空白，以进一步扩大摩尔定律的规模和经济效益。

Proposal ID: 0644316Title: CAREER: A Synergistic CAD Framework for Nanometer Design and ProcessIntegrationPI: David PanInstitution: UT AustinAbstract:After four decades of Moore's Law empowered by CMOS scaling, the semiconductor industry is facing unprecedented design and manufacturing challenges. The industry is stuck with the 193nm optical lithography as the dominant integrated circuit manufacturing process, which is likely to remain so for at least another 5 years, for 45nm, 32nm, and even 22nm technology nodes. A prominent feature of the deep sub-wavelength lithography is its proximity, layout-dependent effect. It is estimated that the lithography and design-related yield losses may contribute to 80% or more of the total yield loss in nanometer designs. However, it is not well captured in existing design flows, from modeling to optimization. This project will develop a synergistic computer aided design (CAD) framework that enables holistic design and process integration. It will resort to the root causes of yield losses by developing a set of design-oriented yet variation-aware manufacturing/yield models, as well as geometrical and electrical characterizations using predictive virtual silicon images. Thus it will help to eliminate significant amount of uncertainties for yield analysis and optimization. Meanwhile, guided by the modeling framework, novel CAD algorithms will be developed at various abstraction levels and architecture explorations will be performed for multi-objective design/manufacturing optimizations. The project will further investigate design and process integration issues for emerging technologies such as nanolithography and hybrid CMOS/post-CMOS processes.The integrated education component of the project will train a diverse body of students in this highly crosscutting and important area, where the intersection and co-evolution of circuit design, CAD and manufacturing create an excellent opportunity for exposing students to multiple engineering disciplines. Taken together in a holistic manner, this project aims at filling the critical gaps between design/CAD and manufacturing/process to further extend the scaling and economic benefits of the Moore's Law.