SHF: Small: Design/Technology Co-Optimization and Exploration in Emerging Scaling

随着半导体行业达到10 nm/7 nm技术节点及以上，更多的创新将通过替代或新兴的缩放实现，如新工艺/材料和器件工程，以寻求等效的缩放效果。这种规模化需要更紧密的设计和技术共同优化和探索。该项目将寻求开发新的CAD算法，工具和方法，以弥合未来集成电路设计和技术差距，在新兴的缩放新时代。这项研究如果成功，将对价值3500亿美元的半导体行业产生巨大影响，该行业正处于从传统规模向新兴规模过渡的关键时刻。PI将与行业合作者合作进行技术转让，以造福整个行业和社会。这项研究的高度跨学科性质将紧密结合到课程开发和学生培训/推广活动。要解决的技术问题包括：（1）新的亚分辨率定向自组装（DSA）图案化和布局协同优化;（2）考虑新兴工艺/材料和设计要求的未来混合光刻技术的新掩模和布局优化;（3）未来标准单元和布线架构探索;（4）下一代纳米器件的物理设计。

As the semiconductor industry reaches 10nm/7nm technology nodes and beyond, more innovations will be realized through alternative or emerging scaling such as novel process/material and device engineering to seek equivalent scaling effects. Such scaling demands closer design and technology co-optimization and explorations. This project will seek to develop novel CAD algorithms, tools, and methodologies to bridge the future IC design and technology gaps in the new era of emerging scaling. The proposed research, if successful, will have tremendous impacts on the $350 billion semiconductor industry which is at a critical point, transitioning from conventional scaling to emerging scaling. The PI will work with industry collaborators for technology transfer to benefit the overall industry and society. The highly interdisciplinary nature of this research will be tightly integrated into curriculum development and student training/outreach activities. The technical problems to be addressed include: (1) new sub-resolution directed-self-assembly (DSA) patterning and layout co-optimizations; (2) new mask and layout optimizations for future hybrid lithography technologies considering emerging processes/materials and design requirements; (3) future standard cell and routing architecture exploration; (4) physical design for next-generation nano-devices.