CSR: Medium: Multicore Real Time Virtual Partitions

多核计算机芯片对硬实时系统提出了新的挑战，因为处理核心之间的复杂的时间耦合共享最后一级缓存，共享内存驱动带宽和共享I/O带宽。该项目通过1)集成资源分区机制及其实现，2)优化资源分配算法，以及3)开发可调度性分析技术来在每个核心上创建实时虚拟分区（rtvp）来解决这一挑战。我们的目标是使每个RTVP都能够像一个独立的单核芯片一样进行分析，独立于其他内核和分区中的工作负载。在多核芯片中，任务的最坏情况执行时间（WCET）取决于分区分配的内存驱动程序带宽、最后一级缓存大小和I/O带宽。为了优化分配给RTVP的资源，需要知道RTVP中的任务在给定的资源分配下是否可调度。要执行可调度性分析，需要知道任务的wcet。要确定任务的wcet，需要知道分配给RTVP的资源。本项目打破这种循环依赖的方法是首先找到一个初始悲观但可行的解，然后应用交互优化方法找到一个接近最优解。我国拥有大量经过认证的实时安全和关键任务软件，这些软件是为单核芯片开发的，使用的是为单核芯片开发的认证程序。现在那些芯片已经过时了，新的芯片被设计成具有更慢的时钟速率但多核。如果没有RTVP这样的技术，一个核心中工作负载的变化可能会对其他核心中任务的可调度性产生不利影响，从而触发其他核心中应用程序的重新认证。这种重新认证的时间和成本在经济上是不可持续的。这个问题对飞机工业来说尤为关键。为了确保该项目的研究成果的可用性，项目团队与飞思卡尔半导体公司（其多核芯片广泛用于航空电子设备）、洛克希德马丁公司（为美国国防部开发基于多核芯片的航空电子设备）、罗克韦尔柯林斯公司（与波音公司和美国联邦航空局合作开发和认证基于多核芯片的民用航空电子设备）以及联邦航空局进行了合作。研究的关键要素将被纳入主办机构的教育计划。

Multicore computer chips pose new challenges for hard real-time systems, because of the complex temporal coupling between processing cores' shared last level cache, shared memory driver bandwidth, and shared I/O bandwidth. The project addresses this challenge by 1) integrating resource partition mechanisms and their implementation, 2) optimizing resource allocation algorithms, and 3) developing schedulability analysis technology to create real time virtual partitions (RTVPs) on each core. The goal is for each RTVP to be able to be analyzed as if it were a standalone single core chip, independent of the workloads in other cores and partitions. In a multicore chip, a task's worst case execution time (WCET) depends on the partition's allocated memory driver bandwidth, the last level cache size, and I/O bandwidth. To optimize the resources allocated to a RTVP, one needs to know if the tasks in the RTVP are schedulable with a given resource allocation. To perform schedulability analysis, one needs to know tasks' WCETs. To determine tasks' WCETs, one needs to know the resources allocated to the RTVP. The approach taken by this project to break such circular dependency is to first find an initial pessimistic but feasible solution, then apply an interactive optimization method to find a near optimal solution. Our nation has a large body of certified real time safety and mission critical software developed for single core chips, using certification procedures developed for single core chips. Now those chips are becoming obsolete, and newer chips are being designed with slower clock rates but multiple cores. Without a technology like RTVP, the change of workload in one core could adversely impact the schedulability of tasks in other cores, triggering the recertification of applications in other cores. The time and costs of such recertification is economically unsustainable. This problem is especially critical for the aircraft industry. To help ensure the usability of this project's research outcomes, the project team has collaborative contacts with Freescale Semiconductor whose multicore chips are widely used in avionics, Lockheed Martin who develops multicore chip based avionics for the US Department of Defense, and with Rockwell Collins who cooperates with Boeing and the FAA on the development and certification of multicore chip based civilian avionics, as well as the FAA. Key elements of the research are to be incorporated into the educational program of the host institution.