SHF: Small: Novel Techniques for Handling Memory Model Bugs

随着并行体系结构的无处不在，编写具有高性能和跨平台可移植性的正确并行程序的重担落在了程序员的肩上。不幸的是，大多数程序员发现这是一项具有挑战性的任务。造成这一挑战的主要问题之一是定义内存操作顺序的底层内存一致性模型涉及的错综复杂的问题。公共体系结构供应商提供的内存模型规范往往含糊不清、难以使用，甚至不正确，这一事实使情况变得更加糟糕。这个项目着眼于描述、检测和避免由内存模型引起的错误的技术。内存模型构成了编写并行程序的基本基础。如果程序员不注意底层内存模型的约束，并行程序可能最终会出现细微的错误。在一种情况下，错误可能会导致程序执行具有不直观的指令交错，这最终会导致不正确的行为和缺乏可移植性。在其他情况下，这些错误可能会导致程序显著减慢并降低可伸缩性。不幸的是，这些错误被称为内存模型错误，很少受到研究界的关注。因此，这项工作的重点是开发新的技术来处理这些错误。这项工作将首先描述现实世界代码库中不同的内存模型错误。这些发现将有助于开发硬件和编译器技术(例如，新的硬件模块、异常、静态分析器等)。来检测和避免这些漏洞。最后，这项工作将集中在设计新的软件调试工具，以帮助程序员摆脱这些微妙的错误。该提案中的研究将通过解决一些最难处理的并发错误来实现并行编程的广泛实践。一方面，它将鼓励软件和硬件公司投资于调试和避免这些漏洞的新技术。另一方面，它将有助于使C++和Java内存模型变得简单和健壮。

With the ubiquitous availability of parallel architectures, the burden falls on programmers' shoulders to write correct parallel programs that have high performance and portability across different platforms. Unfortunately, most programmers find it a challenging task. One of the major issues that contribute to this challenge is the intricacies involved with the underlying memory consistency models that define the order of memory operations. The situation is worsened by the fact that the memory model specifications provided by public architecture vendors are often ambiguous, difficult to use, and even incorrect. This project looks at techniques to characterize, detect and avoid bugs caused by memory models. A memory model forms the fundamental basis for writing parallel programs. If a programmer is not careful about the constraints of the underlying memory model, a parallel program might end up having subtle bugs. In one scenario, the bugs might cause a program execution to have unintuitive interleaving of instructions, which eventually leads to incorrect behavior and lack of portability. In other scenarios, the bugs might cause a significant slowdown and poor scalability of the program. Unfortunately these bugs, referred to as Memory Model Bugs, receive very little attention from the research community. Therefore, this work focuses on developing new techniques to deal with these bugs. The work will first characterize different memory model bugs in real world code bases. The findings will be useful in developing hardware and compiler techniques (e.g., new hardware modules, exceptions, static analyzers, etc.) to detect as well as avoid these bugs. Finally, the work will focus on designing new software debugging tools to help programmers get rid of these subtle bugs. The research in this proposal will enable the widespread practice of parallel programming by addressing some of the hardest concurrency bugs. On one hand, it will encourage software and hardware companies to invest in new techniques for debugging and avoiding these bugs. On the other hand, it will help make C++ and Java memory models simple and robust.