GOALI: Power-Efficient, High-Resolution, Analog-to-Digital Converter for Broadband Applications

提案编号：1404890GOALI：高能效、高分辨率、模数转换器用于射频数字应用，低功耗数字化高达1 GHz的带宽Jose Silva-Martinez德克萨斯A&A&Amp；M大学摘要：该项目承诺通过开发一种具有无与伦比的架构的新型模数转换器来提高实际模拟信号的功率效率、带宽和分辨率处理，这将对延长电子设备的电池寿命和可靠性产生重大影响，并有可能降低芯片上混合模式系统的生产成本。目前，超过27亿用户需要数万亿比特每秒的全球网络容量。在cmos技术中，更小的特征尺寸的晶体管允许在单个芯片中实现更多的数字功能，使得在最近被禁止的更复杂的信号处理算法的物理实现成为可能。“一体式”移动系统显然正在成为首选的通信来源。例如，为下一代蜂窝电话开发了新兴的长期演进(LTE)标准，以分配更多和更快的服务。新部署的数字电视频道的完全数字化、高分辨率图像识别以及一些军事应用等应用需要宽带和高分辨率数字转换器，通常需要超过12个有效位数。该项目是迈向多种服务数字化的一步。消费电子、无线通信和图像处理行业以及国土安全和军事部门将受益于高分辨率宽带实时数字转换器的开发。该项目旨在满足未来多标准应用需求，推出一款工作在GHz频率范围内的新型高效、高分辨率模数转换器(ADC)。该项目的目标是开发一种ADC体系结构，利用最少的数字资源，以适度的功耗将高达1 GHz的带宽数字化。提出的时间交错ADC结构将采用四个流水线子ADC，每个ADC以500MS/S的速度运行，以每秒2x109个信号采样的速率实现12个有效位数的分辨率，同时总功耗低于500 mW。这将通过利用非常快的(40 nm或更高)CMOS技术、开发更好的线性度的高效校准方案以及整合适用于高分辨率、低功耗宽带应用的创新IC设计技术来实现。输入信号由四个独立的通道并行处理，从而放宽了对每个通道的要求。这种方法的主要缺点是系统线性度以及系统性能受到通道之间不可避免的失配的限制。采样输入信号时的不准确是对系统分辨率的另一个相关限制。这项研究将开发创新的解决方案来解决这些现有的障碍，并将重点放在将校准方案与直通增益有限但高度线性的放大阶段相结合，从而产生更环保的解决方案。高增益放大器将在可能的情况下避免使用，因为它们耗电量大且带宽有限。为了进一步改善子ADC的线性度和降低系统功耗，将使用一种新的高效剩余曲线。所提出的架构是实现高效的RF-数字信息转换器的相关步骤，最大限度地减少了噪声和不准确的模拟硬件的使用。

Proposal No:1404890GOALI: Power-Efficient, High-Resolution, Analog-to-Digital Converter for RF-to-Digital Applications That Digitize Up to 1 GHz Bandwidth with Low Power ConsumptionJose Silva-MartinezTexas A&M UniversityAbstract:This project promises to improve the power efficiency, bandwidth and resolution of real-world analog signals with processing made possible by the development of a novel analog-to-digital converter with an unmatched architecture that will have a significant impact on extending the battery lifetime and reliability of electronic devices, and it also has the potential to reduce the production cost of mixed-mode systems on chips. Currently more than 2.7 billion users demand a global network capacity of several trillions of bits per second. Smaller feature size transistors in CMOS technology allow more digital functions in a single chip making possible the physical realization of more complex signal processing algorithms that were prohibited in the recent past. The "All in One" mobile systems are clearly becoming the preferred source of communication. For instance, emerging Long-Term Evolution (LTE) standards for the next generation of cellular phones have been developed to allocate more and faster services. Applications such as entire digitization of the newly deployed digital TV channels, high resolution image recognition as well as a number of military applications require wide-band and high resolution digitizers, usually requiring over 12 effective number of bits. This project is a step towards the digitization of multiple services. Consumer electronics, wireless communication and image processing industries as well as homeland security and military sectors will benefit from the development of high-resolution broadband real-time digitizers.This project is designed to meet future multi-standard application demands with a new highly efficient, high-resolution analog-to-digital converter (ADC) operating in the GHz frequency range. The aim of this project is to develop an ADC architecture that digitizes up to 1 GHz bandwidth with modest power consumption, utilizing minimal digital resources. The proposed time interleave ADC architecture will employ four pipeline sub-ADCs, running at 500 MS/s each to achieve a resolution of 12 effective number of bits at a rate of 2x109 signal samples per second while overall power dissipation is under 500mWatts. This will be possible by leveraging a very fast (40 nm or more) CMOS technology, developing an efficient calibration scheme for better linearity and integrating innovative IC design techniques suitable for high-resolution low-power broadband applications. The input signal is processed by four independent channels that operate in parallel, which then relaxes the requirements for every channel. The main drawback of this approach is the fact that system linearity, and so system performance, is limited by unavoidable mismatches between channels. Inaccuracies when sampling the input signal represents another relevant limitation to system resolution. This research will develop innovative solutions to resolve these existing hurdles and will focus on combining the calibration schemes with through limited-gain but highly-linear amplification stages that should result in greener solutions. High-gain amplifiers will be avoided when possible since they are power hungry and their bandwidth is limited. A new efficient residue curve will be used to further improve sub-ADCs linearity and reduce system power consumption. The proposed architecture is a relevant step towards the realization of efficient RF-to-digital information converters, minimizing the use of noisy and inaccurate analog hardware.